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| HT46RU25/HT46CU25 A/D Type 8-Bit MCU Technical Document * Tools Information * FAQs * Application Note - HA0004E HT48 & HT46 MCU UART Software Implementation Method - HA0005E Controlling the I2C bus with the HT48 & HT46 MCU Series - HA0013E HT48 & HT46 LCM Interface Design - HA0047E An PWM application example using the HT46 series of MCUs Features * Operating voltage: * Up to 0.5ms instruction cycle with 8MHz system clock fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V * System clock (fSYS): 400kHz~8MHz, 32.768kHz * 48 bidirectional I/O lines (max.) * One interrupt input shared with an I/O line * One 8-bit and two 16-bit programmable timer/event at VDD=5V * 16-level subroutine nesting * 8-channels 12-bit resolution A/D converter * 4-channels (6+2)/(7+1)-bit PWM output shared with four I/O lines * Universal Asynchronous Receiver Transmitter counter with prescaler and PFD (programmable frequency divider) function and overflow interrupt * 16K16 program memory in two banks (Bank 0, 1) * 5768 (1923) data memory RAM (UART) * Bit manipulation instruction * 16-bit table read instruction * 63 powerful instructions * All instructions in one or two machine cycles * Low voltage reset function * I2C Bus (slave mode) * 48/56-pin SSOP package (address from 040H~0FFH, bank 0~2) * On-chip crystal and RC oscillator * Watchdog Timer * Supports PFD for sound generation * Real Time Clock (RTC) with 8-bit prescaler * HALT function and wake-up feature reduce power consumption General Description The HT46RU25/HT46CU25 are 8-bit, high performance, RISC architecture microcontroller devices specifically designed for A/D applications that interface directly to analog signals, such as those from sensors. The mask version HT46CU25 is fully pin and functionally compatible with the OTP version HT46RU25 device. The advantages of low power consumption, I/O flexibility, programmable frequency divider, timer functions, oscillator options, multi-channel A/D Converter, Pulse Width Modulation function, UART function, I2C interface, HALT and wake-up functions, enhance the versatility of these devices to suit a wide range of A/D application possibilities such as sensor signal processing, motor driving, industrial control, consumer products, subsystem controllers, etc. I2C is a trademark of Philips Semiconductors. Rev. 1.30 1 March 9, 2007 HT46RU25/HT46CU25 Block Diagram TM R2C TM R2 M U P r e s c a le r X TM R2 fS YS In te rru p t C ir c u it STACK P ro g ra m EPROM P ro g ra m C o u n te r IN T C TM R0C TM R0 PFD0 TM R1C TM R1 PFD1 W DT M M U P r e s c a le r X TM R0 TM R1 fS YS U X fS YS /4 BP In s tr u c tio n R e g is te r MP M U X DATA M e m o ry T im e B ase RTC PA5 PGC PG M U fS X YS /4 W DT OSC OSC3 OSC4 W DT OSC In s tr u c tio n D ecoder ALU T im in g G e n e ra to r MUX P o rt G PG 0~PG 7 STATUS PFC PF PW M P o rt F S h ifte r PF0~PF7 OSC2 OSC4 OS RE VD VS OS S S D C1 ACC H ALT LVR E N /D IS PDC PD P o rt D P D 0 /P W M 0 ~ P D 3 /P W PD 4~PD 7 M3 C3 U AR T Bus PCC PC 8 -C h a n n e l A /D C o n v e rte r PBC PB PAC PA I2 C B u s S la v e M o d e P o rt C PC PC PC PC PC 0/ 1/ 2~ 6/ 7/ TX RX PC5 OSC3 OSC4 P o rt B P B 0 /A N 0 ~ P B 7 /A N 7 PA PA PA PA PA PA 0~ 3/ 4 5/ 6/ 7/ PA2 PFD IN T SDA SCL P o rt A Rev. 1.30 2 March 9, 2007 HT46RU25/HT46CU25 Pin Assignment P B 5 /A N 5 P B 4 /A N 4 P A 3 /P F D PA2 P B 5 /A N 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 P B 4 /A N 4 P A 3 /P F D PA2 PA1 PA0 P B 3 /A N 3 P B 2 /A N 2 P B 1 /A N 1 P B 0 /A N 0 TM R2 PF3 PF2 PF1 PD7 PD6 PD5 PD4 VSS PF0 TM R0 P C 0 /T X P C 1 /R X PC2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 P B 6 /A N 6 P B 7 /A N 7 PA4 P A 5 /IN T P A 6 /S D A P A 7 /S C L PF4 PF5 PF6 PF7 OSC2 OSC1 VDD RES TM R1 P D 3 /P W M 3 P D 2 /P W M 2 P D 1 /P W M 1 P D 0 /P W M 0 P C 7 /O S C 4 P C 6 /O S C 3 PC5 PC4 PC3 PA1 PA0 P B 3 /A N 3 P B 2 /A N 2 P B 1 /A N 1 P B 0 /A N 0 TM R2 PF3 PF2 PF1 PD7 PD6 PD5 PD4 VSS PF0 TM R0 P C 0 /T X P C 1 /R X PC2 PG0 PG1 PG2 PG3 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 8 7 6 5 4 3 2 1 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 P B 6 /A N 6 P B 7 /A N 7 PA4 P A 5 /IN T P A 6 /S D A P A 7 /S C L PF4 PF5 PF6 PF7 OSC2 OSC1 VDD RES TM R1 P D 3 /P W M 3 P D 2 /P W M 2 P D 1 /P W M 1 P D 0 /P W M 0 P C 7 /O S C 4 P C 6 /O S C 3 PC5 PC4 PC3 PG7 PG6 PG5 PG4 H T 4 6 R U 2 5 /H T 4 6 C U 2 5 4 8 S S O P -A H T 4 6 R U 2 5 /H T 4 6 C U 2 5 5 6 S S O P -A Rev. 1.30 3 March 9, 2007 HT46RU25/HT46CU25 Pin Description Pin Name PA0~PA2 PA3/PFD PA4 PA5/INT PA6/SDA PA7/SCL I/O Options Description Bidirectional 8-bit input/output port. Each bit can be configured as wake-up input by option (bit option). Software instructions determine the CMOS output or Schmitt trigger input with or without pull-high resistor (determine by pull-high options: bit option). The PFD and INT are pin-shared with PA3 and PA5, respectively. Once the I2C Bus function is used, the internal registers related to PA6 and PA7 cannot be used. Bidirectional 8-bit input/output port. Software instructions determine the CMOS output, Schmitt trigger input with or without pull-high resistor (determined by pull-high option: bit option) or A/D input. Once a PB line is selected as an A/D input (by using software control), the I/O function and pull-high resistor are automatically disabled. Pull-high Wake-up I/O PA3 or PFD I/O or I2C Bus PB0/AN0~ PB7/AN7 I/O Pull-high PC0/TX PC1/RX PC2~PC5 PC6/OSC3 PC7/OSC4 I/O Bidirectional 8-bit input/output port. Software instructions determine the CMOS output, Schmitt trigger input with or without pull-high resistor (determine by pull-high option: byte option). Pull-high TX and RX are pin-shared with PC0 and PC1, once the UART Bus function I/O or UART is used, the internal registers related to PC0 and PC1 cannot be used. OSC3/OSC4 Software instructions determine the UART function to be used. OSC3/OSC4 are pin shared with PC6/PC7. (depending on the OSC type option) Bidirectional 8-bit input/output port. Software instructions determine the CMOS output, Schmitt trigger input with or without a pull-high resistor (determined by pull-high option: byte option). The PWM0/PWM1/PWM2/ PWM3 output function are pin-shared with PD0/PD1/PD2/PD3 (depending on the PWM options). Bidirectional 8-bit input/output port. Software instructions determine the CMOS output, Schmitt trigger input with or without pull-high resistor (determine by pull-high option: byte option). Bidirectional 8-bit input/output port. Software instructions determine the CMOS output, Schmitt trigger input with or without pull-high resistor (determine by pull-high option: byte option). Timer/Event Counter 0 Schmitt trigger input (without pull-high resistor) Timer/Event Counter 1 Schmitt trigger input (without pull-high resistor). Timer/Event Counter 2 Schmitt trigger input (without pull-high resistor). Schmitt trigger reset input, active low Negative power supply, ground Positive power supply OSC1 and OSC2 are connected to an RC network or a crystal (by options) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock. PD0/PWM0 PD1/PWM1 PD2/PWM2 PD3/PWM3 PD4~PD7 PF0~PF7 I/O Pull-high PWM I/O Pull-high PG0~PG7 (56-pin package only) I/O I I I I 3/4 3/4 I O Pull-high 3/4 3/4 3/4 3/4 3/4 3/4 Crystal or RC TMR0 TMR1 TMR2 RES VSS VDD OSC1 OSC2 Absolute Maximum Ratings Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................150mA Total Power Dissipation .....................................500mW Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C IOH Total............................................................-100mA Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.30 4 March 9, 2007 HT46RU25/HT46CU25 D.C. Characteristics Test Conditions Symbol Parameter VDD VDD Operating Voltage Operating Current (Crystal OSC, RC OSC) Operating Current (Crystal OSC, RC OSC) Operating Current (Crystal OSC, RC OSC) Operating Current (Crystal OSC, RC OSC) Operating Current (fSYS=RTC OSC) Standby Current (WDT Enabled) Standby Current (WDT Disabled) Low Voltage Reset Voltage I/O Port Sink Current 5V IOH 3V I/O Port Source Current 5V RPH VAD IADC DNL INL 3V Pull-high Resistance 5V A/D Input Voltage Additional Power Consumption if A/D Converter is Used ADC Differential Non-Linear ADC Integral Non-Linear 3/4 3V 5V 3/4 3/4 No load No load 3/4 3/4 3/4 3/4 VOH=0.9VDD 3/4 3V 5V 3V 5V 5V 5V 3V 5V 3V 5V 3V 5V 3/4 3V VOL=0.1VDD Conditions fSYS=4MHz fSYS=8MHz No load, fSYS=4MHz, ADC Off, UART Off No load, fSYS=4MHz, ADC Off, UART On No load, fSYS=8MHz, ADC Off, UART Off No load, fSYS=8MHz, ADC Off, UART On No load, ADC Off, UART Off No load, system HALT, UART Off No load, system HALT, UART Off 3/4 2.2 3.3 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 2.7 4 10 -2 -5 20 10 0 3/4 3/4 3/4 3/4 3/4 3/4 1 2.5 1.5 3 4 5 0.3 0.6 3/4 3/4 3/4 3/4 3 8 20 -4 -10 60 30 3/4 0.5 1.5 3/4 2.5 5.5 5.5 2 5 3 6 8 10 0.6 1 5 10 1 2 3.3 3/4 3/4 3/4 3/4 100 50 VDD 1 3 2 4 V V mA mA mA mA mA mA mA mA mA mA mA mA V mA mA mA mA kW kW V mA mA LSB LSB Min. Typ. Max. Unit Ta=25C IDD1 IDD2 IDD3 IDD4 IDD5 ISTB1 ISTB2 VLVR IOL Rev. 1.30 5 March 9, 2007 HT46RU25/HT46CU25 A.C. Characteristics Test Conditions Symbol Parameter VDD fSYS1 System Clock System Clock (32768Hz Crystal OSC) RTC Frequency Timer I/P Frequency (TMR0, TMR1, TMR2) Watchdog Oscillator Period 5V tRES tSST tLVR tINT tAD tADC tADCS tIIC External Reset Low Pulse Width System Start-up Timer Period Low Voltage Width to Reset Interrupt Pulse Width A/D Clock Period A/D Conversion Time A/D Sampling Time I2C Bus Clock Period 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3V Conditions 2.2V~5.5V 3.3V~5.5V 2.2V~5.5V 3/4 2.2V~5.5V 3.3V~5.5V 3/4 3/4 3/4 Power-up or Wake-up from HALT 3/4 3/4 3/4 3/4 3/4 Connect to external pull-high resistor 2kW 400 400 3/4 3/4 0 0 45 32 1 3/4 0.25 1 1 3/4 3/4 64 3/4 3/4 32768 32768 3/4 3/4 90 65 3/4 1024 1 3/4 3/4 80 32 3/4 4000 8000 3/4 3/4 4000 8000 180 130 3/4 3/4 2 3/4 3/4 3/4 3/4 3/4 kHz kHz Hz Hz kHz kHz ms ms ms *tSYS ms ms ms tAD tAD *tSYS Min. Typ. Max. Unit Ta=25C fSYS2 tRTCOSC fTIMER tWDTOSC Note: *tSYS=1/fSYS Rev. 1.30 6 March 9, 2007 HT46RU25/HT46CU25 Functional Description Execution Flow The system clock is derived from either a crystal or an RC oscillator or an 32768Hz crystal. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. The pipelining scheme makes it possible for each instruction to be effectively executed in a cycle. If an instruction changes the value of the program counter, two cycles are required to complete the instruction. S y s te m C lo c k T1 T2 T3 T4 T1 Program Counter - PC The program counter (PC) is 14 bits wide and it controls the sequence in which the instructions stored in the program ROM are executed. The contents of the PC can specify a maximum of 1638416 addresses. After accessing a program memory word to fetch an instruction code, the value of the PC is incremented by 1. The PC then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading a PCL register, a subroutine call, an initial reset, an internal interrupt, an external interrupt, or returning from a subroutine, the PC T2 T3 T4 T1 T2 T3 T4 O S C 2 ( R C o n ly ) PC PC PC+1 PC+2 F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 ) F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C ) F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 ) Execution Flow Program Counter *13 0 0 0 0 0 0 0 *12 0 0 0 0 0 0 0 *11 0 0 0 0 0 0 0 *10 0 0 0 0 0 0 0 *9 0 0 0 0 0 0 0 *8 0 0 0 0 0 0 0 *7 0 0 0 0 0 0 0 *6 0 0 0 0 0 0 0 *5 0 0 0 0 0 0 0 *4 0 0 0 0 1 1 1 *3 0 0 1 1 0 0 1 *2 0 1 0 1 0 1 0 *1 0 0 0 0 0 0 0 *0 0 0 0 0 0 0 0 Mode Initial Reset External Interrupt Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow UART Bus Interrupt I C Bus Interrupt Multi-function Interrupt Skip Loading PCL Jump, Call Branch Return from Subroutine 2 Program Counter + 2 (Within the current bank) *13 *12 *11 *10 *9 #9 S9 *8 #8 S8 @7 @6 @5 @4 @3 @2 @1 @0 #7 S7 #6 S6 #5 S5 #4 S4 #3 S3 #2 S2 #1 S1 #0 S0 BP.5 #12 #11 #10 S13 S12 S11 S10 Program Counter Note: *13~*0: Program counter bits #12~#0: Instruction code bits 1312 87 P ro g ra m BP .5 S13~S0: Stack register bits @7~@0: PCL bits 0 C o u n te r B a n k P o in te r (B P ) Rev. 1.30 7 March 9, 2007 HT46RU25/HT46CU25 manages the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get a proper instruction; otherwise proceed to the next instruction. The lower byte of the PC (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination is within 256 locations. When a control transfer takes place, an additional dummy cycle is required. Program Memory - EPROM The program memory (EPROM) is used to store the program instructions, which are to be executed. It also contains data, table, and interrupt entries, and is organized into 1638416 bits format which are addressed by the program counter and table pointer. The ROM memory is divided into two banks (Bank0 and Bank1). Each ROM 000H 004H 008H 00CH 010H 014H 018H D e v ic e In itia liz a tio n P r o g r a m E x te r n a l In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e U A R T B u s In te r r u p t S u b r o u tin e I2C B u s In te r r u p t S u b r o u tin e P ro g ra m M e m o ry bank has 819216 bit and is selected by setting the bank pointer (BP.5; Bank0, BP=000XXXXXB; Bank1: BP=001XXXXXB). The JMP and CALL instructions provide only 13 bits of address to allow branching within any 8K program memory. When doing a JMP or CALL instruction, the user must ensure that the bank pointer bit (BP.5) is programmed so that the desire program memory bank is addressed. If a return from a CALL instruction or interrupt is executed, the entire 14 bit program counter is popped off the stack. Therefore, manipulation of the BP.5 is not required for the RET or RETI instructions. Certain locations in the ROM are reserved for special usage: * Location 000H Location 000H is reserved for program initialization. After a chip reset, the program always begins execution at this location. * Location 004H Location 004H is reserved for the external interrupt service program. If the INT input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 004H. * Location 008H Location 008H is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H. * Location 00CH M u lti- fu n c tio n In te r r u p t S u b r o u tin e n00H nFFH L o o k - u p T a b le ( 2 5 6 w o r d s ) Location 00CH is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH. * Location 010H 1F00H 1FFFH L o o k - u p T a b le ( 2 5 6 w o r d s ) 1 6 b its N o te : n ra n g e s fro m 0 to 1 F Location 010H is reserved for the UART Bus interrupt service program. If the UART Bus interrupt resulting from transmission flag or reception is completed, and if the interrupt is enabled and the stack is not full, the program begins execution at location 010H. Program Memory Table Location Instruction *13~*8 TABRDC [m] TABRDL [m] TBHP 111111 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0 Table Location Note: *13~*0: Table location bits @7~@0: Table pointer bits TBHP: Table pointer higher-order bits Rev. 1.30 8 March 9, 2007 HT46RU25/HT46CU25 * Location 014H This area is reserved for the I2C Bus interrupt service program. If the I2C Bus interrupt resulting from a slave address is matched or has completed one byte of data transfer, and if the interrupt is enabled and the stack is not full, the program begins execution at location 014H. * Location 018H Data Memory - RAM The data memory (RAM) has a structure of 6288 bits, and is divided into two functional groups, namely; special function registers (528 bits) and general purpose data memory (5768 bits) most of which are readable/writeable, although some are read only. The general purpose data memory is divided into three banks (Bank0~Bank2), each bank contains 1928 bits. Bank0 can be read from and written to by directly addressing or indirectly addressing mode using MP0, Bank1 and Bank2 can be read from and written to only by indirect addressing mode using MP1. The special function registers are overlapped in all banks. The unused space before 40H is reserved for future expansion use and reading these locations returns the result 00H. The space before 40H is overlapping in each bank. The general purpose data memory, addressed from 40H to FFH (Bank0; BP=0 , Bank1; BP=1 or Bank2; BP=2), is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through memory pointer registers (MP0;01H/MP1;03H). The space before 40H is overlapping in each bank. Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the RAM pointed to by MP0 (01H) and MP1(03H) respectively. Reading location 00H or 02H indirectly returns the result 00H. While writing, it indirectly leads to no operation. The function of data movement between two indirect addressing registers is not supported. The memory pointer registers, MP0 and MP1, are both 8-bit registers used to access the RAM by combining corresponding indirect addressing registers. Accumulator - ACC The accumulator is closely related to ALU operations. It is also mapped to location 05H of the RAM and capable of operating with immediate data. The data movement between two data memory locations must pass through the accumulator. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions: * Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) This area is reserved for the Multi-function interrupt service program. If a timer interrupt results from a Timer/Event Counter 2 overflow, or a real time clock time-out, or Time base time-out, and if the interrupt is enable and the stack is not full, the program begins execution at location 018H. * Table location Any location in the ROM can be used as a look-up table. The instructions TABRDC [m] (page specified by TBHP) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the contents of the higher-order byte to TBLH (Table Higher-order byte register) (08H). Only the destination of the lower-order byte in the table is well-defined; the other bits of the table word are all transferred to the lower portion of TBLH. The TBLH is read only, the higher-order byte table pointer TBHP (1FH) and the lower-order byte table pointer TBLP (07H) are read/write registers, indicating the table location. Before accessing the table, the location the location has to be placed in TBHP and TBLP. All the table related instructions require 2 cycles to complete the operation. These areas may function as a normal ROM depending upon the users requirements. Stack Register - STACK The stack register is a special part of the memory used to save the contents of the program counter. The stack is organized into 16 levels and is neither part of the data nor part of the program, and is neither readable nor writeable. Its activated level is indexed by a stack pointer (SP) and is neither readable nor writeable. At the start of a subroutine call or an interrupt acknowledgment, the contents of the program counter is pushed onto the stack. At the end of the subroutine or interrupt routine, signaled by a return instruction (RET or RETI), the contents of the program counter is restored to its previous value from the stack. If the stack is full and an enabled interrupt occurs, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. Rev. 1.30 9 March 9, 2007 HT46RU25/HT46CU25 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 3FH 40H TM R2 TM R2C M F IC USR UCR1 UCR2 T X R /R X R BRG In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 BP ACC PCL TBLP TBLH RTCC STATUS IN T C 0 TM R0H TM R0L TM R0C TM R1H TM R1L TM R1C PA PAC PB PBC PC PCC PD PDC PW M0 PW M1 PW M2 PW M3 IN T C 1 TBHP HADR HCR HSR HDR ADRL ADRH ADCR ACSR PF PFC PG PGC S p e c ia l P u r p o s e D a ta M e m o ry * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ) The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS The status register (0AH) is 8 bits wide and contains, a carry flag (C), an auxiliary carry flag (AC), a zero flag (Z), an overflow flag (OV), a power down flag (PDF), and a Watchdog time-out flag (TO). It also records the status information and controls the operation sequence. Except for the TO and PDF flags, bits in the status register can be altered by instructions similar to other registers. Data written into the status register does not alter the TO or PDF flags. Operations related to the status register, however, may yield different results from those intended. The TO and PDF flags can only be changed by a Watchdog Timer overflow, chip power-up, or clearing the Watchdog Timer and executing the HALT instruction. The Z, OV, AC, and C flags reflect the status of the latest operations. On entering the interrupt sequence or executing the subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly. Interrupts - INTC0, INTC1, MFIC The device provides one external interrupt, two internal timer/event counter 0/1 interrupts, UART Bus interrupt, I 2 C-Bus interrupt, the Multi-function interrupt (timer/event counter 2 interrupt, real time clock interrupt, time base interrupt), The interrupt control register 0 (INTC0;0BH), interrupt control register 1 (INTC1;1EH) and Multi-Function interrupt control register (MFIC;2FH) contains the interrupt control bits to set the enable/disable and the interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC0, INTC1 and MFIC may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register FFH G e n e ra l P u rp o s e D a ta M e m o ry (3 B a n k s : B a n k 0 , B a n k 1 , B a n k 2 ) :U nused R e a d a s "0 0 " RAM Mapping Rev. 1.30 10 March 9, 2007 HT46RU25/HT46CU25 Bit No. 0 Label C Function C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared by a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status (0AH) Register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. External interrupts are triggered by a high to low transition of the INT and the related interrupt request flag (EIF; bit 4 of the INTC0) will be set. When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be cleared to disable other interrupts. The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (T0F; bit 5 of the INTC0), which is normally caused by a timer overflow. After the interrupt is enabled, and the stack is not full, and the T0F bit is set, a subroutine call to location 08H occurs. The related interrupt request flag (T0F) is reset, and the EMI bit is cleared to disable further mask-able interrupts. The Timer/Event Counter 1 and Timer/Event Counter 2 operated in the same manner, The Timer/Event Counter 1 related interrupt request flag is T1F (bit 6 of the INTC0) and its subroutine call location is 0CH. The Timer/Event Counter 2 related interrupt request flag are MFF(bit 6 of the INTC1) and T2F (bit 4 of the MFIC), and its subroutine call location is 018H. The related interrupt request flag (MFF) will be reset and the EMI bit cleared to disable further interrupts. T2F (bit 4 of the MFIC) will not be cleared automatically, it should be cleared by user. The UART Bus interrupt is initialized by setting the UART Bus interrupt request flag (URIF; bit 4 of the INTC1), caused by a Transmit enable (TXIF) or one byte of data receive is completed (RXIF) or transmit Idle (TIDF) is set or receive idle (RIDF) is set. When the interrupt is enabled, the stack is not full and the TXIF or RXIF or TIDF or RIDF bit is set, a subroutine call to location 010H will occur. The related interrupt request flag (URIF) will be reset and the EMI bit cleared to disable further interrupts. Rev. 1.30 11 The I2C Bus interrupt is initialized by setting the I2C Bus interrupt request flag (HIF; bit 5 of the INTC1), caused by a slave address match (HAAS=1) or one byte of data transfer is completed. When the interrupt is enabled, the stack is not full and the HIF bit is set, a subroutine call to location 014H will occur. The related interrupt request flag (HIF) will be reset and the EMI bit cleared to disable further interrupts. The Multi-Function Interrupt (MFI) is initialized by setting the interrupt request flag (MFF; bit 6 of the INTC1), that is caused by a timer 2 overflow (T2F; bit 4 of the MFIC), caused by a regular real time clock time-out (RTF; bit 6 of the MFIC) or caused by a time base time-out (TBF; bit5 of the MFIC). After the interrupt is enabled (EMFI=1), the stack is not full, and the MFF bit is set, a subroutine call to location 018H will occur. The related interrupt request flag (MFF) is reset and the EMI bit is cleared to disable further maskable interrupts. T2F, TBF and RTF indicate that a related interrupt has occurred, these flags will not be cleared automatically after reading these flags, they should be cleared by user. During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, RET or RETI may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. 1 2 3 4 5 6, 7 AC Z OV PDF TO 3/4 March 9, 2007 HT46RU25/HT46CU25 Interrupt Source External Interrupt Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow UART Bus Interrupt I2C Bus Interrupt Multi-function Interrupt (Timer/event counter 2 / Real time clock / Time base overflow) Priority 1 2 3 4 5 6 Vector 04H 08H 0CH 10H 14H 18H Once the interrupt request flags, composed of EIF, T0F, T1F, URIF, HIF and MFF, are set, they will remain in the INTC0 and INTC1 registers until the interrupts are serviced or cleared by a software instruction. It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the CALL operates in the interrupt subroutine. Bit No. 0 1 2 3 4 5 6 7 Label EMI EEI ET0I ET1I EIF T0F T1F 3/4 Function Controls the master (global) interrupt (1=enable; 0= disable) Controls the external interrupt (1=enable; 0=disable) Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable) Controls the Timer/Event Counter 1 interrupt (1=enable; 0=disable) External interrupt request flag (1=active; 0=inactive) Internal Timer/Event Counter 0 request flag (1=active; 0=inactive) Internal Timer/Event Counter 1 request flag (1=active; 0=inactive) For test mode used only. Must be written as 0; otherwise may result in unpredictable operation. INTC0 (0BH) Register Bit No. 0 1 2 3, 7 4 5 6 Label EURI EHI EMFI 3/4 URIF HIF MFF Function Control the UART interrupt (1=enable; 0=disable) Control the I2C Bus interrupt (1=enable; 0=disable) Control the Multi-function interrupt (1=enable; 0=disable) Unused bit, read as 0 UART request flag (1=active; 0=inactive) I2C Bus interrupt request flag (1=active; 0=inactive) Multi-function interrupt request flag (1=active; 0=inactive) INTC1 (1EH) Register Bit No. 0 1 2 3, 7 4 5 6 Label ET2I ETBI ERTI 3/4 T2F TBF RTF Function Control the Timer/Event Counter 2 interrupt (1=enable; 0=disable) Control the time base interrupt (1=enable; 0=disable) Control the real time clock interrupt (1=enable; 0=disable) Unused bit, read as 0 Timer/Event Counter 2 interrupt request flag (1=active; 0=inactive) Time base interrupt request flag (1=active; 0=inactive) Real time clock interrupt request flag (1=active; 0=inactive) MFIC (2FH) Register Rev. 1.30 12 March 9, 2007 HT46RU25/HT46CU25 Oscillator Configuration There are three oscillator circuits in the microcontroller. The device provides three oscillator circuits for system clocks, i.e., RC oscillator, crystal oscillator and 32768Hz crystal oscillator, determined by options. No matter what type of oscillator is selected, the signal is used for the system clock. The HALT mode stops the system oscillator (RC and crystal oscillator only) and ignores external signal in order to conserve power. The 32768Hz crystal oscillator still runs at HALT mode. If the 32768Hz crystal oscillator is selected as the system oscillator, the system oscillator is not stopped but the instruction execution is stopped. Since the 32768Hz oscillator is also designed for timing purposes, the internal timing (RTC, time base, WDT) operation still runs even if the system enters the HALT mode. If an RC oscillator is used, an external resistor between OSC1 and VSS is required and the resistance must range from 30kW to 750kW. The system clock, divided by 4, is available on OSC2 with pull-high resistor, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of oscillation may vary with VDD, temperatures and the chip itself due to process variations. It is, therefore, not suitable for timing sensitive operations where an accurate oscillator frequency is desired. If a Crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. Instead of a crystal, a resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors between OSC1 and OSC2 are required (If the oscillating frequency is less than 1MHz). There is another oscillator circuit designed for the real time clock. In this case, only the 32.768kHz crystal oscillator can be applied. The crystal should be connected between OSC3 and OSC4. The RTC oscillator circuit can be controlled to oscillate quickly by setting the QOSC bit (bit 4 of RTCC). It is recommended to turn on the quick oscillating function upon power on, and then turn it off after 2 seconds. The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the power down mode, the system clock is stopped, but the WDT oscillator still works within a period of approximately 65ms at 5V. The WDT oscillator can be disabled by option to conserve power. If the 32768Hz crystal oscillator is selected as the system oscillator, the clock source (fS) is implemented by a real time clock oscillator (RTC Oscillator) Watchdog Timer - WDT The WDT clock is sourced from its own dedicated RC oscillator (WDT oscillator), the instruction clock (system clock divided by 4) or the RTC oscillator, the choice of which is determined by configuration options. This timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. The watchdog timer can be disabled by option. If the watchdog timer is disabled, all executions related to the WDT result in no operation. V OSC3 OSC1 DD 470pF OSC1 OSC4 3 2 7 6 8 H z C r y s ta l/R T C O s c illa to r OSC2 C r y s ta l O s c illa to r fS YS /4 RC OSC2 O s c illa to r System Oscillator Note: The external resistor and capacitor components connected to the 32768Hz crystal are not necessary to provide oscillation. For applications where precise RTC frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. S y s te m RTC OSC C lo c k /4 32768H z 12kH z W DT OSC ROM Code O p tio n fs D iv id e r fs/2 8 W D T P r e s c a le r CK R T CK R T T im e 2 1 5/fS 2 1 4/fS 2 1 3/fS 2 1 2/fS -o ~ ~ ~ ~ ut 21 21 21 21 6 5 M a s k O p tio n W D T C le a r R eset /fS /fS 4 /fS 3 /fS Watchdog Timer Rev. 1.30 13 March 9, 2007 HT46RU25/HT46CU25 Once an internal WDT oscillator (RC oscillator with period 65ms at 5V normally) is selected, it is divided by 212~215 (by option to get the WDT time-out period). The WDT time-out minimum period is 300ms~600ms. This time-out period may vary with temperature, VDD and process variations. By selection from the WDT option, longer time-out periods can be achieved. If the WDT time-out is selected at 215, the maximum time-out period is divided by 215~216 which is about 2.1s~4.3s. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operates in the same manner except that in the HALT state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock. The WDT overflow under normal operation will initialize a chip reset and set the status bit TO. Whereas in the HALT mode, the overflow will initialize a warm reset and only the program counter and stack pointer are reset to zero. To clear the contents of the WDT, three methods are adopted; external reset (a low level to RES), software instructions, or a HALT instruction. The software instructions include CLR WDT and the other set CLR WDT1 and CLR WDT2. Of these two types of instruction, only one can be active depending on the option - CLR WDT times selection option. If the CLR WDT is selected (i.e. CLRWDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In case CLR WDT1 and CLR WDT2 are chosen (i.e. CLRWDT times equal two), these two instructions must be executed to clear the WDT, otherwise, the WDT may reset the chip due of time-out. If the WDT time-out period is selected at fs/212 (option), the WDT time-out period ranges from fs/212~fs/213, since the CLR WDT or CLR WDT1 and CLR WDT2 instructions only clear the last two stages of the WDT. Time Base The time base offers a periodic time-out period to generate a regular internal interrupt. Its time-out period ranges from 212/fS to 215/fS selected by options. If time base time-out occurs, the related interrupt request flags (MFF bit 6 of the INTC1, TBF; bit 5 of the MFIC) are set. If the interrupts (EMFI and ETBI) are enabled, and the stack is not full, a subroutine call to location 18H occurs. TBF will not be cleared automatically, it should be cleared by user. Real Time Clock - RTC The real time clock (RTC) is operated in the same manner as the time base that is used to supply a regular internal interrupt. Its time-out period ranges from fS/28 to fS/215 by software programming. Writing data to RT2, RT1 and RT0 (bits 2, 1, 0 of the RTCC; 09H) yields various time-out periods. If the RTC time-out occurs, the related interrupt request flags (MFF bit 6 of INTC1, RTF; bit 6 of MFIC) are set. If the interrupts (EMFI and ERTI) are enabled, and the stack is not full, a subroutine call to location 18H occurs. RTF will not be cleared automatically, it should be cleared by user. Bit No. 0 1 2 3 4 5~7 Label RT0 RT1 RT2 3/4 Function 8 to 1 multiplexer control inputs to select the real clock prescaler output Unused bit, read as 0 32768Hz OSC quick start-up oscillating 0/1: quick/slow start Unused bit, read as 0 QOSC 3/4 RTCC (09H) Register fS YS /4 W D T O s c illa to r RTC O s c illa to r C o n fig u r a tio n O p tio n S e le c t fS C o n fig u r a tio n O p tio n D iv id e b y 2 1 2 ~ 2 1 5 T im e B a s e In te r r u p t 2 12/fS ~ 2 15/fS Time Base fS RTC YS /4 W D T O s c illa to r O s c illa to r C o n fig u r a tio n O p tio n S e le c t fS D iv id e b y 2 8 ~ 2 (S e t b y R T C C R e g is te r s ) R T2~R T0 15 R T C In te rru p t 2 8/fS ~ 2 15/fS Real Time Clock Rev. 1.30 14 March 9, 2007 HT46RU25/HT46CU25 RT2 0 0 0 0 1 1 1 1 RT1 0 0 1 1 0 0 1 1 RT0 0 1 0 1 0 1 0 1 RTC Clock Divided Factor 2 8* 2 9* 210* 2* 212 2 13 11 the actual interrupt subroutine execution is delayed by more than one cycle. However, if the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. Reset There are three ways in which a reset may occur: * RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation 214 2 15 Note: * not recommended to be used Power Down Operation - HALT The HALT mode is initialized by the HALT instruction and results in the following: * The system oscillator is turned off but the WDT oscil- * * * * lator keeps running (if the WDT oscillator or the real time clock is selected). The contents of the on-chip RAM and registers remain unchanged. The WDT will be cleared and start recounting (if the WDT clock source is from the WDT oscillator or the real time clock). All of the I/O ports maintain their original status. The PDF flag is set and the TO flag is cleared. The WDT time-out during HALT differs from other chip reset conditions, for it can perform a warm reset that resets only the program counter and SP, leaving the other circuits in their original state. Some registers remain unaffected during other reset conditions. Most registers are reset to the initial condition when the reset conditions are met. Examining the PDF and TO flags, the program can distinguish between different chip resets. V DD 0 .0 1 m F * 100kW RES 10kW 0 .1 m F * The system quits the HALT mode by way of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a warm reset. After examining the TO and PDF flags, the cause for a chip reset can be determined. The PDF flag is cleared by system power-up or by executing the CLR WDT instruction and is set when executing the HALT instruction. On the other hand, the TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, and leaves the other circuits in their original status. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it awakens from an interrupt, two sequences may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. But if the interrupt is enabled and the stack is not full, the regular interrupt response takes place. When an interrupt request flag is set to 1 before entering the HALT mode, the wake-up function of the related interrupt will be disabled. If a wake-up event occurs, it takes 1024 fSYS (system clock period) to resume normal operation. In other words, a dummy period is inserted after a wake-up. If the wake-up results from an interrupt acknowledge signal, Reset Circuit Note: * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. HALT W DT RES W DT T im e - o u t R eset W a rm R eset E x te rn a l C o ld R eset OSC1 SST 1 0 - b it R ip p le C o u n te r P o w e r - o n D e te c tio n Reset Configuration VDD RES S S T T im e - o u t C h ip R eset tS ST Reset Timing Chart Rev. 1.30 15 March 9, 2007 HT46RU25/HT46CU25 TO 0 u 0 1 1 PDF 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT tents of the lower-order byte buffer to TMR0H (TMR1H) and TMR0L (TMR1L) registers, respectively. The Timer/Event Counter 1/0 preload register is changed by each writing TMR0H (TMR1H) operations. Reading TMR0H (TMR1H) will latch the contents of the TMR0H (TMR1H) and TMR0L (TMR1L) counters to the destination and the lower-order byte buffer, respectively. Reading the TMR0L (TMR1L) will read the contents of the lower-order byte buffer. Writing TMR2 makes the starting value be placed in the timer/event counter 2 preload register and reading TMR2 gets the contents of the timer/event counter 2. The TMR0C (TMR1C,TMR2C) is the Timer/Event Counter 0 (1,2) control register, which defines the operating mode, counting enable or disable and an active edge. The T0M0, T0M1 (TMR0C), T1M0, T1M1 (TMR1C) and T2M0, T2M1 (TMR2C) bits define the operation mode. The event count mode is used to count external events, which means that the clock source is from an external (TMR0, TMR1, TMR2) pin. The timer mode functions as a normal timer with the clock source coming from the internal selected clock source. Finally, the pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR0, TMR1, TMR2), and the counting is based on the internal selected clock source. In the event count or timer mode, the Timer/Event Counter 0 (1) starts counting at the current contents in the timer/event counter and ends at FFFFH. The Timer/Event counter 2 starts counting at the current contents in the timer/event counter and ends at FFH. Once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag (T0F; bit 5 of the INTC0, T1F; bit 6 of the INTC0, MFF; bit 6 of the INTC1 and T2F; bit 4 of the MFIC). In the pulse width measurement mode with the values of the T0ON/T1ON/T2ON and T0E/T1E/T2E bits equal to 1, after the TMR0/TMR1/TMR2 has received a transient from low to high (or high to low if the T0E/T1E/T2E bit is 0), it will start counting until the TMR0/TMR1/ TMR2) returns to the original level and resets the T0ON/T1ON/T2ON (T0ON; bit 4 of the TMR0C, T1ON; bit 4 of the TMR1C, or T2ON; bit 4 of the TMR2C). The measured result remains in the timer/event counter even if the activated transient occurs again. In other words, only 1-cycle measurement can be made until the T0ON/T1ON/T2ON is set. The cycle measurement will re-function as long as it receives further transient pulse. In this operation mode, the timer/event counter begins counting not according to the logic level but to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an interrupt request, as in the other two modes, i.e., event and timer modes. Note: u stands for unchanged To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system awakes from a HALT state or during power up. Awaking from a HALT state or system power up, an SST delay is added. An extra SST delay is added during power up period, and any wake-up from HALT may enable only the SST delay. The functional unit chip reset status are shown below. Program Counter Interrupt Prescaler, Divider WDT Timer/event Counter Input/output Ports Stack Pointer Timer/Event Counter Two Timer/Event Counters (TMR0,TMR1, TMR2) are implemented in the microcontroller. The timer/event counter 0 contains a 16-bit programmable count-up counter and the clock may come from an external source or an internal clock source. An internal clock source comes from fSYS. The Timer/Event counter 1 contains a 16-bit programmable count-up counter and the clock may come from an external source or an internal clock source. An internal clock source comes from fSYS/4. The Timer/Event Counter 2 contains an 8-bit programmable count-up counter and the clock may come from an external source or an internal clock source. An internal clock source comes from fSYS. The external clock input allows the user to count external events, measure time intervals or pulse widths, or generate an accurate time base. There are eight registers related to the Timer/Event Counter 0; TMR0H (0CH), TMR0L (0DH), TMR0C (0EH) and the Timer/Event Counter 1; TMR1H (0FH), TMR1L (10H), TMR1C (11H) and the Timer/Event Counter 2; TMR2 (2CH) TMR2C (2DH). Writing TMR0L (TMR1L) will only put the written data to an internal lower-order byte buffer (8-bit) and writing TMR0H (TMR1H) will transfer the specified data and the con000H Disable Cleared Clear. After a master reset, WDT begins counting Off Input mode Points to the top of the stack Rev. 1.30 16 March 9, 2007 HT46RU25/HT46CU25 The registers states are summarized in the following table. Register Program Counter MP0 MP1 BP ACC TBLP TBLH RTCC STATUS INTC0 TMR0H TMR0L TMR0C TMR1H TMR1L TMR1C PA PAC PB PBC PC PCC PD PDC PWM0 PWM1 PWM2 PWM3 INTC1 TBHP HADR HCR HSR HDR ADRL ADRH ADCR ACSR Reset (Power On) 000H xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx --00 0111 --00 xxxx -000 0000 xxxx xxxx xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -000 -000 xxxx xxxx xxxx xxx0--0 0--100- -0-1 xxxx xxxx xxxx ---xxxx xxxx 0100 0000 1--- --00 WDT Time-out RES Reset (Normal Operation) (Normal Operation) 000H xxxx xxxx xxxx xxxx 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu --00 0111 --1u uuuu -000 0000 xxxx xxxx xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -000 -000 uuuu uuuu xxxx xxx0--0 0--100- -0-1 xxxx xxxx xxxx ---xxxx xxxx 0100 0000 1--- --00 000H xxxx xxxx xxxx xxxx 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu --00 0111 --uu uuuu -000 0000 xxxx xxxx xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -000 -000 uuuu uuuu xxxx xxx0--0 0--100- -0-1 xxxx xxxx xxxx ---xxxx xxxx 0100 0000 1--- --00 RES Reset (HALT) 000H xxxx xxxx xxxx xxxx 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu --00 0111 --01 uuuu -000 0000 xxxx xxxx xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -000 -000 uuuu uuuu xxxx xxx0--0 0--100- -0-1 xxxx xxxx xxxx ---uuuu uuuu 0100 0000 1--- --00 WDT Time-out (HALT)* 000H uuuu uuuu uuuu uuuu 00u0 00uu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu --11 uuuu -uuu uuuu uuuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uu-u u--uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu -uuu uuuu uuuu uuuu uuuu--u u--uuuu uuuu uuuu uuuu uuuu ---uuuu uuuu uuuu uuuu u--- --uu Rev. 1.30 17 March 9, 2007 HT46RU25/HT46CU25 Register PF PFC PG PGC TMR2 TMR2C MFIC USR UCR1 UCR2 TXR/RXR BRG Note: Reset (Power On) 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx 00-0 1000 -000 -000 0000 1011 0000 00x0 0000 0000 xxxx xxxx xxxx xxxx * stands for warm reset u stands for unchanged x stands for unknown WDT Time-out RES Reset (Normal Operation) (Normal Operation) 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx 00-0 1000 -000 -000 0000 1011 0000 00x0 0000 0000 xxxx xxxx xxxx xxxx 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx 00-0 1000 -000 -000 0000 1011 0000 00x0 0000 0000 xxxx xxxx xxxx xxxx RES Reset (HALT) 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx 00-0 1000 -000 -000 0000 1011 0000 00x0 0000 0000 xxxx xxxx xxxx xxxx WDT Time-out (HALT)* uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu-u uuuu -uuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu xxxx PW M (6 + 2 ) o r (7 + 1 ) C o m p a re fS YS T o P D 0 /P D 1 /P D 2 /P D 3 C ir c u it D a ta B u s L o w B y te B u ffe r 8 - s ta g e P r e s c a le r 8 -1 M U X T0PSC 2~T0PSC 0 TM R0 T0E T0M 1 T0M 0 T0O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l f IN T T0M 1 T0M 0 1 6 - B it P r e lo a d R e g is te r R e lo a d H ig h B y te Low B y te O v e r flo w to In te rru p t 1 6 - B it T im e r /E v e n t C o u n te r PFD0 Timer/Event Counter 0 D a ta B u s L o w B y te B u ffe r T fS YS /4 f IN TM R1 T1E T1M 1 T1M 0 T1O N T1M 1 T1M 0 1 6 - B it P r e lo a d R e g is te r P u ls e W id th M e a s u re m e n t M o d e C o n tro l R e lo a d H ig h B y te Low B y te O v e r flo w to In te r r u p t 1 6 - B it T im e r /E v e n t C o u n te r PFD1 Timer/Event Counter 1 Rev. 1.30 18 March 9, 2007 HT46RU25/HT46CU25 fS YS 8 - s ta g e P r e s c a le r 8 -1 M U X T2PSC 2~T2PSC 0 (1 /1 ~ 1 /1 2 8 ) TM R2 T2E T2M 1 T2M 0 T2O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l 8 - B it T im e r /E v e n t C o u n te r (T M R 2 ) O v e r flo w to In te rru p t f IN T D a ta B u s T2M 1 T2M 0 8 - B it T im e r /E v e n t C o u n te r P r e lo a d R e g is te r R e lo a d Timer/Event Counter 2 PFD0 M PFD1 U X 1 /2 PFD P A 3 D a ta C T R L PFD S o u r c e O p tio n PFD Source Option To enable the counting operation, the Timer ON bit (T0ON; bit 4 of the TMR0C, T1ON; bit 4 of the TMR1C, or T2ON; bit 4 of the TMR2C) should be set to 1. In the pulse width measurement mode, the T0ON/T1ON/ T2ON is automatically cleared after the measurement cycle is completed. But in the other two modes, the T0ON/T1ON/T2ON can only be reset by instructions. The overflow of the Timer/Event Counter 0/1/2 is one of the wake-up sources, and Timer/Event Counter 0/1 can also be applied to a PFD (Programmable Frequency Divider) output at PA3 by options. No matter what the operation mode is, writing a 0 to ET0I, ET1I or ET2I disables the related interrupt service. When the PFD function is selected, executing the SET [PA].3 instruction will enable the PFD output and executing the CLR [PA].3 instruction will disable the PFD output. In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the timer/event counter is turn on, data written to the timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still continues to operate until an overflow occurs. When the timer/event counter (reading TMR0/TMR1/ TMR2) is read, the clock is blocked to avoid errors, as this may results in a counting error. Blocking of the clock should be taken into account by the programmer. It is strongly recommended to load a desired value into the TMR0/TMR1/TMR2 register first, before turning on the related timer/event counter, for proper operation since the initial value of the TMR0/TMR1/TMR2 is unknown. Due to the timer/event scheme, the programmer should pay special attention on the instruction to enable then disable the timer for the first time, whenever there is a need to use the timer/event function, to avoid unpredictable result. After this procedure, the timer/event function can be operated normally. The bit0~bit2 of the TMR0C/TMR2C (T0PSC2~0/ T2PSC2~0) can be used to define the pre-scaling stages of the internal clock sources of the timer/event counter. The definitions are as shown. The overflow signal of the timer/event counter can be used to generate the PFD signal. The timer prescaler is also used as the PWM counter. Rev. 1.30 19 March 9, 2007 HT46RU25/HT46CU25 Bit No. Label Function Defines the prescaler stages, T0PSC2, T0PSC1, T0PSC0= 000: fINT=fSYS 001: fINT=fSYS/2 010: fINT=fSYS/4 011: fINT=fSYS/8 100: fINT=fSYS/16 101: fINT=fSYS/32 110: fINT=fSYS/64 111: fINT=fSYS/128 Defines the TMR0 active edge of the timer/event counter: In Event Counter Mode (T0M1,T0M0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (T0M1,T0M0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge Enable/disable timer counting (0=disable; 1=enable) Unused bit, read as 0 Defines the operating mode, T0M1, T0M0: 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR0C (0EH) Register 0 1 2 T0PSC0 T0PSC1 T0PSC2 3 T0E 4 5 T0ON 3/4 6 7 T0M0 T0M1 Bit No. 0~2 Label 3/4 Unused bit, read as 0 Function 3 T1E Defines the TMR1 active edge of the timer/event counter: In Event Counter Mode (T1M1,T1M0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (T1M1,T1M0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge Enable/disable timer counting (0=disabled; 1=enabled) Unused bit, read as 0 Defines the operating mode, T1M1, T1M0: 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR1C (11H) Register 4 5 T1ON 3/4 6 7 T1M0 T1M1 Rev. 1.30 20 March 9, 2007 HT46RU25/HT46CU25 Bit No. Label Function Defines the prescaler stages, T2PSC2, T2PSC1, T2PSC0= 000: fINT=fSYS 001: fINT=fSYS/2 010: fINT=fSYS/4 011: fINT=fSYS/8 100: fINT=fSYS/16 101: fINT=fSYS/32 110: fINT=fSYS/64 111: fINT=fSYS/128 Defines the TMR2 active edge of the timer/event counter: In Event Counter Mode (T2M1,T2M0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (T2M1,T2M0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge Enable/disable timer counting (0=disable; 1=enable) Unused bit, read as 0 Defines the operating mode, T2M1, T2M0: 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR2C (2EH) Register 0 1 2 T2PSC0 T2PSC1 T2PSC2 3 T2E 4 5 T2ON 3/4 6 7 T2M0 T2M1 Input/Output Ports There are 48 bidirectional input/output lines in the microcontroller, labeled as PA, PB, PC, PD, PF and PG, which are mapped to the data memory of [12H], [14H], [16H], [18H], [28H] and [2AH] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H, 16H, 18H, 28H or 2AH). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PCC, PDC, PFC, PGC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control register must write a 1. The input source also depends on the control register. If the control register bit is 1, the input will read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in the read-modify- write instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H, 17H, 19H, 29H and 2BH. After a chip reset, these input/output lines remain at high levels or floating state (depending on pull-high options). Each bit of these input/output latches can be set or cleared by SET [m].i and CLR [m].i (m=12H, 14H, 16H, 18H, 28H or 2AH) instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. Each I/O port has a pull-high option. Once the pull-high option is selected, the I/O port has a pull-high resistor, otherwise, theres none. Take note that a non-pull-high I/O port operating in input mode will cause a floating state. The PA3 and PA5 are pin-shared with the PFD and INT pins respectively. If the PFD option is selected, the output signal in output mode of PA3 will be the PFD signal generated by the timer/event counter overflow signal. The input mode always remain in its original functions. Once the PFD option is selected, the PFD output signal is controlled by the PA3 data register only. Writing a 1 to the PA3 data register will enable the PFD output function and writing 0 will force the PA3 to remain at 0. Rev. 1.30 21 March 9, 2007 HT46RU25/HT46CU25 V C o n tr o l B it D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r D CK Q S Q P u ll- h ig h O p tio n PA0 PA4 PA6 PB0 PC2 PC6 PD0 PD4 PF0 PG0 M U X ~PA ,PA /S D /A N ~PC /O S /P W ~PD ~PF ~PG 2 , P A 3 /P F D 5 /IN T A , P A 7 /S C L 0 ~ P B 7 /A N 7 5 C 3 , P C 7 /O S C 4 M 0 ~ P D 3 /P W M 3 7 7 7 DD D a ta B it Q D CK S Q W r ite D a ta R e g is te r [P A 3 , P F D ] o r [P D 0 ,P W M 0 ] o r [P D 1 ,P W M 1 ] o r [P D 2 ,P W M 2 ] o r [P D 3 ,P W M 3 ] R e a d D a ta R e g is te r S y s te m W a k e -u p ( P A o n ly ) IN T fo r P A 5 O n ly M U X E N (P F D o r PW M 0~PW M 3) W a k e - u p O p tio n Input/Output Ports V C o n tr o l B it D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t P C 0 /T X R e a d C o n tr o l R e g is te r D a ta B it Q D CK S Q M F ro m UART TX M U X R e a d D a ta R e g is te r U X & TXEN D CK S Q Q P u ll- h ig h O p tio n DD W r ite D a ta R e g is te r UARTEN PC0/TX Input/Output Ports V C o n tr o l B it D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r P C 1 /R X D a ta B it Q D CK S Q D CK S Q Q P u ll- h ig h O p tio n DD W r ite D a ta R e g is te r M U R e a d D a ta R e g is te r To UART RX X PC1/RX Input/Output Ports Rev. 1.30 22 March 9, 2007 HT46RU25/HT46CU25 The I/O functions of PA3 are shown below. I/O I/P Mode (Normal) PA3 Note: Logical Input O/P (Normal) Logical Output I/P (PFD) Logical Input O/P (PFD) PFD (Timer on) of the PWM counter comes from fSYS. The PWM registers are four 8-bit registers. The waveforms of the PWM outputs are as shown. Once the PD0/PD1/PD2/PD3 are selected as the PWM outputs and the output function of the PD0/PD1/PD2/PD3 are enabled (PDC.0/PDC.1/ PDC.2/PDC.3 =0), writing 1 to PD0/PD1/PD2/PD3 data register will enable the PWM output function and writing 0 will force the PD0/PD1/PD2/PD3 to remain at 0. A (6+2) bits mode PWM cycle is divided into four modulation cycles (modulation cycle 0~modulation cycle 3). Each modulation cycle has 64 PWM input clock period. In a (6+2) bit PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM register is denoted by DC which is the value of PWM.7~PWM.2. The group 2 is denoted by AC which is the value of PWM.1~PWM.0. In a (6+2) bits mode PWM cycle, the duty cycle of each modulation cycle is shown in the table. Parameter AC (0~3) i The definitions of PFD control signal and PFD output frequency are listed in the following table. PA3 Timer Data Timer Preload Value Register Off Off On On Note: X X N N 0 1 0 1 PA3 Pad State 0 U 0 PFD PFD Frequency X X X fTMR/[2(m-n)] X stands for unused U stands for unknown M is 65536 for Timer0, Timer1 PFD, 256 for Timer2 PFD N is preload value for timer/event counter fTMR is the input clock frequency for the timer/event counter The PB can also be used as A/D converter inputs. The A/D function will be described later. There is a PWM function shared with PD0/PD1/PD2/PD3. If the PWM function is enabled, the PWM0/PWM1/PWM2/PWM3 signal will appear on PD0/PD1/PD2/PD3 (if PD0/PD1/ PD2/PD3 is operating in output mode). The I/O functions of PD0/PD1/PD2/PD3 are as shown. I/O Mode PD0 PD1 PD2 PD3 I/P O/P (Normal) (Normal) Logical Input Logical Output I/P (PWM) Logical Input O/P (PWM) PWM0 PWM1 PWM2 PWM3 A (7+1) bits mode PWM cycle is divided into two modulation cycles (modulation cycle0~modulation cycle 1). Each modulation cycle has 128 PWM input clock period. In a (7+1) bits PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM register is denoted by DC which is the value of PWM.7~PWM.1. The group 2 is denoted by AC which is the value of PWM.0. In a (7+1) bits mode PWM cycle, the duty cycle of each modulation cycle is shown in the table. Parameter AC (0~1) i The modulation frequency, cycle frequency and cycle duty of the PWM output signal are summarized in the following table. PWM Modulation Frequency fSYS/64 for (6+2) bits mode fSYS/128 for (7+1) bits mode PWM Cycle PWM Cycle Frequency Duty fSYS/256 [PWM]/256 Rev. 1.30 23 March 9, 2007 HT46RU25/HT46CU25 fS YS /2 [P W M ] = 1 0 0 PW M [P W M ] = 1 0 1 PW M [P W M ] = 1 0 2 PW M [P W M ] = 1 0 3 PW M PW M 2 6 /6 4 m o d u la tio n p e r io d : 6 4 /fS M o d u la tio n c y c le 0 YS 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4 2 6 /6 4 2 6 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4 2 6 /6 4 M o d u la tio n c y c le 1 PW M 2 6 /6 4 M o d u la tio n c y c le 2 c y c le : 2 5 6 /fS YS 2 5 /6 4 M o d u la tio n c y c le 3 2 6 /6 4 M o d u la tio n c y c le 0 (6+2) PWM Mode fS YS /2 [P W M ] = 1 0 0 PW M [P W M ] = 1 0 1 PW M [P W M ] = 1 0 2 PW M [P W M ] = 1 0 3 PW M 5 2 /1 2 8 PW M m o d u la tio n p e r io d : 1 2 8 /fS M o d u la tio n c y c le 0 PW M c y c le : 2 5 6 /fS YS YS 5 0 /1 2 8 5 0 /1 2 8 5 0 /1 2 8 5 1 /1 2 8 5 0 /1 2 8 5 1 /1 2 8 5 1 /1 2 8 5 1 /1 2 8 5 1 /1 2 8 5 1 /1 2 8 5 2 /1 2 8 M o d u la tio n c y c le 1 M o d u la tio n c y c le 0 (7+1) PWM Mode A/D Converter The 8 channels and 12-bit resolution A/D converter are implemented in this microcontroller. The reference voltage is VDD. The A/D converter contains 4 special registers which are; ADRL (24H), ADRH (25H), ADCR (26H) and ACSR (27H). The ADRH and ADRL are A/D result register higher-order byte and lower-order byte and are read-only. After the A/D conversion is completed, the ADRH and ADRL should be read to get the conversion result data. The ADCR is an A/D converter control register, which defines the A/D channel number, analog channel select, start A/D conversion control bit and the end of A/D conversion flag. If the users want to start an A/D conversion. Define PB configuration, select the converted analog channel, and give START bit a raising edge and falling edge (0(R)1(R)0). At the end of A/D conversion, the EOCB bit is cleared. The ACSR is A/D clock setting register, which is used to select the A/D clock source. The A/D converter control register is used to control the Rev. 1.30 24 A/D converter. The bit2~bit0 of the ADCR are used to select an analog input channel. There are a total of eight channels to select. The bit5~bit3 of the ADCR are used to set PB configurations. PB can be an analog input or as digital I/O line decided by these 3 bits. Once a PB line is selected as an analog input, the I/O functions and pull-high resistor of this I/O line are disabled and the A/D converter circuit is powered on. The EOCB bit (bit6 of the ADCR) is end of A/D conversion flag. Check this bit to know when A/D conversion is completed. The START bit of the ADCR is used to begin the conversion of the A/D converter. Giving START bit a rising edge and falling edge means that the A/D conversion has started. In order to ensure the A/D conversion is completed, the START should remain at 0 until the EOCB is cleared to 0 (end of A/D conversion). Bit 7 of the ACSR register is used for test purposes only and must not be used for other purposes by the application program. Bit1 and bit0 of the ACSR register are used to select the A/D clock source. March 9, 2007 HT46RU25/HT46CU25 When the A/D conversion has completed, the A/D interrupt request flag will be set. The EOCB bit is set to 1 when the START bit is set from 0 to 1. Important Note for A/D initialization: Special care must be taken to initialize the A/D converter each time the Port B A/D channel selection bits are modified, otherwise the EOCB flag may be in an undefined condition. An A/D initialization is implemented by setting the START bit high and then clearing it to zero within 10 instruction cycles of the Port B channel selection bits being modified. Note that if the Port B channel selection bits are all cleared to zero then an A/D initialization is not required. Bit No. Label Selects the A/D converter clock source 00= system clock/2 ADCS0 01= system clock/8 ADCS1 10= system clock/32 11= undefined 3/4 TEST Unused bit, read as 0 For test mode use only ACSR (27H) Register Bit No. 0 1 2 3 4 5 6 7 Label ACS0 ACS1 ACS2 PCR0 PCR1 PCR2 EOCB Defines the analog channel select Function Function 0 1 2~6 7 Defines the port B configuration select. If PCR0, PCR1 and PCR2 are all zero, the ADC circuit is powered off to reduce power consumption. Indicates end of A/D conversion. (0 = end of A/D conversion) Each time bits 3~5 change state the A/D should be initialized by issuing a START signal, otherwise the EOCB flag may have an undefined condition. See Important note for A/D initialization. START Starts the A/D conversion. (0(R)1(R)0= start; 0(R)1= Reset A/D converter and set EOCB to 1) ADCR (26H) Register PCR2 0 0 0 0 1 1 1 1 PCR1 0 0 1 1 0 0 1 1 PCR0 0 1 0 1 0 1 0 1 7 PB7 PB7 PB7 PB7 PB7 PB7 PB7 AN7 6 PB6 PB6 PB6 PB6 PB6 PB6 PB6 AN6 5 PB5 PB5 PB5 PB5 PB5 PB5 AN5 AN5 4 PB4 PB4 PB4 PB4 PB4 AN4 AN4 AN4 3 PB3 PB3 PB3 PB3 AN3 AN3 AN3 AN3 2 PB2 PB2 PB2 AN2 AN2 AN2 AN2 AN2 1 PB1 PB1 AN1 AN1 AN1 AN1 AN1 AN1 0 PB0 AN0 AN0 AN0 AN0 AN0 AN0 AN0 Port B Configuration Rev. 1.30 25 March 9, 2007 HT46RU25/HT46CU25 ACS2 0 0 0 0 1 1 1 1 ACS1 0 0 1 1 0 0 1 1 ACS0 0 1 0 1 0 1 0 1 Analog Input Channel Selection Register ADRL ADRH Note: Bit7 D3 D11 Bit6 D2 D10 Bit5 D1 D9 Bit4 D0 D8 Bit3 3/4 D7 Bit2 3/4 D6 Bit1 3/4 D5 Bit0 3/4 D4 Analog Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 D0~D11 is A/D conversion result data bit LSB~MSB. ADRL (24H), ADRH (25H) Register The following programming example illustrates how to setup and implement an A/D conversion. The method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete. Example: using EOCB Polling Method to detect end of conversion clr mov mov mov mov EADI a,00000001B ACSR,a a,00100000B ADCR,a : : ; disable ADC interrupt ; setup the ACSR register to select fSYS/8 as the A/D clock ; setup ADCR register to configure Port PB0~PB3 as A/D inputs ; and select AN0 to be connected to the A/D converter ; As the Port B channel bits have changed the following START ; signal (0-1-0) must be issued within 10 instruction cycles : Start_conversion: clr START set START clr START Polling_EOC: sz EOCB jmp polling_EOC mov a,ADRH mov adrh_buffer,a mov a,ADRL mov adrl_buffer,a : : jmp start_conversion ; reset A/D ; start A/D ; poll the ADCR register EOCB bit to detect end of A/D conversion ; continue polling ; read conversion result high byte value from the ADRH register ; save result to user defined memory ; read conversion result low byte value from the ADRL register ; save result to user defined memory ; start next A/D conversion Rev. 1.30 26 March 9, 2007 HT46RU25/HT46CU25 M in im u m START o n e in s tr u c tio n c y c le n e e d e d , M a x im u m te n in s tr u c tio n c y c le s a llo w e d EOCB PC R2~ PCR0 A /D tA 000B DCS s a m p lin g tim e 100B A /D tA DCS s a m p lin g tim e A /D tA DCS s a m p lin g tim e 000B 1 . P B p o rt s e tu p a s I/O s 2 . A /D c o n v e r te r is p o w e r e d o ff to r e d u c e p o w e r c o n s u m p tio n 100B 101B AC S2~ ACS0 000B P o w e r-o n R eset R e s e t A /D c o n v e rte r 1 : D e fin e P B c o n fig u r a tio n 2 : S e le c t a n a lo g c h a n n e l A /D N o te : A /D tA D tA CS 010B S ta rt o f A /D c o n v e r s io n 000B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n 001B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n d o n 't c a r e E n d o f A /D c o n v e r s io n tA D C c o n v e r s io n tim e tA D C c o n v e r s io n tim e YS A /D tA D C c o n v e r s io n tim e A /D DC c lo c k m u s t b e fS = 3 2 tA D = 8 0 tA D YS /2 , fS /8 o r fS YS /3 2 A/D Conversion Timing Low Voltage Reset - LVR The microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~VLVR, such as changing a battery, the LVR will automatically reset the device internally. The LVR has the same effect or function with the external RES signal which performs a chip reset. During HALT state, LVR is disabled. The LVR includes the following specifications: * The low voltage (0.9V~VLVR) has to remain in their The relationship between VDD and VLVR is shown below. VDD 5 .5 V V OPR 5 .5 V V 3 .0 V 2 .2 V LVR original state for more than 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and do not perform a reset function. * The LVR uses the OR function with the external RES 0 .9 V Note: VOPR is the voltage range for proper chip operation at 4MHz system clock. signal to perform a chip reset. V 5 .5 V DD V LVR L V R D e te c t V o lta g e 0 .9 V 0V R e s e t S ig n a l R eset *1 N o r m a l O p e r a tio n *2 R eset Low Voltage Reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: Since low voltage state has to be maintained in its original state for over 1ms, therefore after a 1ms delay, the device enters the reset mode. Rev. 1.30 27 March 9, 2007 HT46RU25/HT46CU25 I2C Bus Serial Interface I2C Bus is implemented in the device. The I2C Bus is a bidirectional two-wire lines. The data line and clock line are implement in SDA pin and SCL pin. The SDA and SCL are NMOS open drain output pin. They must connect a pull-high resistor respectively. Using the I2C Bus, the device has two ways to transfer data. One is in slave transmit mode, the other is in slave receive mode. There are four registers related to I2C Bus; HADR([20H]), HCR([21H]), HSR([22H]), HDR([23H]). The HADR register is the slave address setting of the device, if the master sends the calling address which match, it means that this device is selected. The HCR is I2C Bus control register which defines the device enable or disable the I2C Bus as a transmitter or as a receiver. The HSR is I2C Bus status register, it responds with the I2C Bus status. The HDR is input/output data register, data to transmit or receive must be via the HDR register. The I2C Bus control register contains three bits. The HEN bit defines whether to enable or disable the I2C Bus. If the data wants to transfer via I2C Bus, this bit must be set. The HTX bit defines whether the I2C Bus is in transmit or receive mode. If the device is as a transmitter, this bit must be set to 1. The TXAK defines the transmit acknowledge signal, when the device received 8-bit data, the device sends this bit to I2C Bus at the 9th clock. If the receiver wants to continue to receive the next data, this bit must be reset to 0 before receiving data. The I2C Bus status register contains 5 bits. The HCF bit is reset to 0 when one data byte is being transferred. If one data transfer is completed, this bit is set to 1. The HAAS bit is set to 1 when the address is matched, and the I2C Bus interrupt request flag is set to 1. If the interrupt is enabled and the stack is not full, a subroutine call to location 10H will occur. Writing data to the I2C Bus control register clears HAAS bit. If the address is not matched, this bit is reset to 0. The HBB bit is set to respond when the I2C Bus is busy. It means that a START signal is detected. This bit is reset to 0 when the I2C Bus is not busy. It means that a STOP signal is detected and the I2C Bus is free. The SRW bit defines the read/write command bit, if the calling address is matched. When HAAS is set to 1, the device checks the SRW bit to determine whether the device is working in transmit or receive mode. When the SRW bit is set to 1, it means that the master wants to read data from the I2C Bus, the slave device must write data to the I2C Bus, so the slave device is working in transmit mode. When SRW is reset to 0, it means that the master wants to write data to the I2C Bus, the slave device must read data from the bus, so the slave device is working in receive mode. The RXAK bit is reset to 0 indicates that an acknowledge signal has been received. In the transmit mode, the transmitter checks the RXAK bit to determine the receiver which wants to receive the next data byte, so the transmitter continues to write data to the I2C Bus until the RXAK bit is set to 1 and the transmitter releases the SDA line, so that the master can send the STOP signal to release the bus. The HADR bit7-bit1 define the device slave address. At the beginning of a transfer, the master must select a device by sending the address of the slave device. The bit 0 is unused and is not defined. If the I2C Bus receives a start signal, all slave device notice the continuity of the 8-bit data. The front of 7 bits is slave address and the first bit is MSB. If the address is matched, the HAAS status bit is set and generates an I2C Bus interrupt. In the ISR, the slave device must check the HAAS bit to determine whether the I2C Bus interrupt comes from the slave address that has matched or completed one 8-bit data transfer. The last bit of the 8-bit data is read/write command bit, it responds in SRW bit. The slave will check the SRW bit to determine whether the master wants to transmit or receive data. The device checks the SRW bit to know if its a transmitter or a receiver. Bit7~Bit1 Slave Address 3/4 means undefined HADR (20H) Register The HDR register is the I2C Bus input/output data register. Before transmitting data, the HDR must write the data which needs to be transmitted. Before receiving data, the device must dummy read data from the HDR. Transmitting or Receiving data from the I2C Bus must be via the HDR register. At the beginning of the transfer of the I2C Bus, the device must initialize the bus, the following are the notes for initializing the I2C Bus: Note: 1: Write the I2C Bus address register (HADR) to define its own slave address. 2: Set HEN bit of the I2C Bus control register (HCR) bit 0 to enable the I2C Bus. 3: Set EHI bit of the interrupt control register 1 (INTC1) bit 0 to enable the I2C Bus interrupt. Bit0 3/4 Rev. 1.30 28 March 9, 2007 HT46RU25/HT46CU25 Bit No. 0~2 3 4 5~6 7 Label 3/4 TXAK HTX 3/4 HEN Unused bit, read as 0 Enable/disable transmit acknowledge (0=acknowledge; 1=dont acknowledge) Defines the transmit/receive mode (0=receive mode; 1=transmit) Unused bit, read as 0 Enable/disable I2C Bus function (0=disable; 1=enable) HCR (21H) Register Bit No. 0 1 2 3~4 5 6 7 Label RXAK 3/4 SRW 3/4 HBB HAAS HCF Function RXAK is cleared to 0 when the master receives an 8-bit data and acknowledgment at the 9th clock, RXAK is set to 1 means not acknowledged. Unused bit, read as 0 SRW is set to 1 when the master wants to read data from the I2C Bus, so the slave must transmit data to the master. SRW is cleared to 0 when the master wants to write data to the I2C Bus, so the slave must receive data from the master. Unused bit, read as 0 HBB is set to 1 when I2C Bus is busy and HBB is cleared to 0 means that the I2C Bus is not busy. HAAS is set to 1 when the calling address has matched, and I2C Bus interrupt will occur and HCF is set. HCF is cleared to 0 when one data byte is being transferred, HCF is set to 1 indicating 8-bit data communication has been finished. HSR (22H) Register Function S ta rt W r ite S la v e A d d re s s to H A D R SET HEN D is a b le CLR EH I P o ll H IF to d e c id e w h e n to g o to I2C B u s IS R I2C B u s In te rru p t= ? E n a b le SET EHI W a it fo r In te r r u p t G o to M a in P r o g r a m G o to M a in P r o g r a m Rev. 1.30 29 March 9, 2007 HT46RU25/HT46CU25 S ta rt No HAAS=1 ? Yes Yes Yes No No HTX=1 ? SRW =1 ? R e a d fro m HDR SET HTX C LR H TX C LR TXAK RETI Yes RXAK=1 ? No C LR H TX C LR TXAK W r ite to H D R W r ite to H D R D um m y R ead F ro m H D R RETI RETI D um m y R ead fro m H D R RETI RETI SCL S ta rt S la v e A d d r e s s SRW ACK SDA 1 0 1 1 0 1 0 1 0 SCL D a ta ACK S to p 1 SDA S=S SA= SR= M =S D=D A=A P=S S ta rt (1 S la v e SRW la v e d a ta (8 C K (R to p (1 SA 0 0 1 0 1 0 0 b it) A d d r e s s ( 7 b its ) b it ( 1 b it) e v ic e s e n d a c k n o w le d g e b it ( 1 b it) b its ) X A K b it fo r tr a n s m itte r , T X A K b it fo r r e c e iv e r 1 b it) b it) SR M D A D A S SA SR M D A D A P I2C Communication Timing Diagram Rev. 1.30 30 March 9, 2007 HT46RU25/HT46CU25 Start Signal The START signal is generated only by the master device. The other device in the bus must detect the START signal to set the I2C Bus busy bit (HBB). The START signal is SDA line from high to low, when SCL is high. SCL SDA Acknowledge Bit One of the slave device generates an acknowledge signal, when the slave address is matched. The master device can check this acknowledge bit to know if the slave device accepts the calling address. If no acknowledge bit, the master must send a STOP bit and end the communication. When the I2C Bus status register bit 6 HAAS is high, it means the address is matched, so the slave must check the SRW as a transmitter (set HTX) to 1 or as a receiver (clear HTX) to 0. SCL Start Bit Slave Address The master must select a device for transferring the data by sending the slave device address after the START signal. All device in the I2C Bus will receive the I2C Bus slave address (7 bits) to compare with its own slave address (7 bits). If the slave address is matched, the slave device will generate an interrupt and save the subsequent bit (8th bit) to the SRW bit and sends an acknowledge bit (low level) to the 9th bit. The slave device also sets the status flag (HAAS), when the slave address is matched. In interrupt subroutine, check the HAAS bit to know whether the I2C Bus interrupt comes from a slave address that is matched or a data byte transfer is completed. When the slave address is matched, the device must be in transmit mode or receive mode and write data to HDR or dummy read from HDR to release the SCL line. SRW Bit The SRW bit means that the master device wants to read from or write to the I2C Bus. The slave device check this bit to understand itself if it is a transmitter or a receiver. The SRW bit is set to 1 means that the master wants to read data from the I2C Bus, so the slave device must write data to a bus as a transmitter. The SRW is cleared to 0 means that the master wants to write data to the I2C Bus, so the slave device must read data from the I2C Bus as a receiver. SDA Stop Bit Data Byte The data is 8 bits and is sent after the slave device has acknowledged the slave address. The first bit is MSB and the 8th bit is LSB. The receiver sends the acknowledge signal (0) and continues to receive the next one byte data. If the transmitter checks and theres no acknowledge signal, then it release the SDA line, and the master sends a STOP signal to release the I2C Bus. The data is stored in the HDR register. The transmitter must write data to the HDR before transmitting data and the receiver must read data from the HDR after receiving data. SCL SDA S to p b it D a ta s ta b le D a ta a llo w change S ta r t b it Data Timing Diagram Receive Acknowledge Bit When the receiver wants to continue to receive the next data byte, it generates an acknowledge bit (TXAK) at the 9th clock. The transmitter checks the acknowledge bit (RXAK) to continue to write data to the I2C Bus or change to receive mode and a dummy reads the HDR register to release the SDA line and the master sends the STOP signal. Rev. 1.30 31 March 9, 2007 HT46RU25/HT46CU25 UART Bus Serial Interface The HT46RU25/HT46CU25 devices contain an integrated full-duplex asynchronous serial communications UART interface that enables communication with external devices that contain a serial interface. The UART function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. The UART function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. * UART features zero. Similarly, the RX pin is the UART receiver pin, which can also be used as a general purpose I/O pin, if the pin is not configured as a receiver, which occurs if the RXEN bit in the UCR2 register is equal to zero. Along with the UARTEN bit, the TXEN and RXEN bits, if set, will automatically setup these I/O pins to their respective TX output and RX input conditions and disable any pull-high resistor option which may exist on the RX pin. * UART data transfer scheme The integrated UART function contains the following features: Full-duplex, asynchronous communication 8 or 9 bits character length Even, odd or no parity options One or two stop bits Baud rate generator with 8-bit prescaler Parity, framing, noise and overrun error detection Support for interrupt on address detect (last character bit=1) Separately enabled transmitter and receiver 2-byte Deep Fifo Receive Data Buffer Transmit and receive interrupts Interrupts can be initialized by the following conditions: - Transmitter Empty Transmitter Idle Receiver Full Receiver Overrun Address Mode Detect The block diagram shows the overall data transfer structure arrangement for the UART. The actual data to be transmitted from the MCU is first transferred to the TXR register by the application program. The data will then be transferred to the Transmit Shift Register from where it will be shifted out, LSB first, onto the TX pin at a rate controlled by the Baud Rate Generator. Only the TXR register is mapped onto the MCU Data Memory, the Transmit Shift Register is not mapped and is therefore inaccessible to the application program. Data to be received by the UART is accepted on the external RX pin, from where it is shifted in, LSB first, to the Receiver Shift Register at a rate controlled by the Baud Rate Generator. When the shift register is full, the data will then be transferred from the shift register to the internal RXR register, where it is buffered and can be manipulated by the application program. Only the RXR register is mapped onto the MCU Data Memory, the Receiver Shift Register is not mapped and is therefore inaccessible to the application program. It should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate TXR and RXR registers, only exists as a single shared register in the Data Memory. This shared register known as the TXR/RXR register is used for both data transmission and data reception. * UART status and control registers * UART external pin interfacing To communicate with an external serial interface, the internal UART has two external pins known as TX and RX. The TX pin is the UART transmitter pin, which can be used as a general purpose I/O pin if the pin is not configured as a UART transmitter, which occurs when the TXEN bit in the UCR2 control register is equal to T r a n s m itte r S h ift R e g is te r MSB LSB CLK TXR R e g is te r B a u d R a te G e n e ra to r T X P in There are five control registers associated with the UART function. The USR, UCR1 and UCR2 registers control the overall function of the UART, while the BRG register controls the Baud rate. The actual data to be transmitted and received on the serial interface is managed through the TXR/RXR data registers. R e c e iv e r S h ift R e g is te r R X P in CLK RXR R e g is te r B u ffe r MSB LSB MCU D a ta B u s UART Data Transfer Scheme Rev. 1.30 32 March 9, 2007 HT46RU25/HT46CU25 * USR register The USR register is the status register for the UART, which can be read by the program to determine the present status of the UART. All flags within the USR register are read only. Further explanation on each of the flags is given below: RXIF flag is cleared when the USR register is read with RXIF set, followed by a read from the RXR register, and if the RXR register has no data available. TXIF The TXIF flag is the transmit data register empty flag. When this read only flag is 0 it indicates that the character is not transferred to the transmit shift registers. When the flag is 1 it indicates that the transmit shift register has received a character from the TXR data register. The TXIF flag is cleared by reading the UART status register (USR) with TXIF set and then writing to the TXR data register. Note that when the TXEN bit is set, the TXIF flag bit will also be set since the transmit buffer is not yet full. TIDLE The TIDLE flag is known as the transmission complete flag. When this read only flag is 0 it indicates that a transmission is in progress. This flag will be set to 1 when the TXIF flag is 1 and when there is no transmit data, or break character being transmitted. When TIDLE is 1 the TX pin becomes idle. The TIDLE flag is cleared by reading the USR register with TIDLE set and then writing to the TXR register. The flag is not generated when a data character, or a break is queued and ready to be sent. RXIF The RXIF flag is the receive register status flag. When this read only flag is 0 it indicates that the RXR read data register is empty. When the flag is 1 it indicates that the RXR read data register contains new data. When the contents of the shift register are transferred to the RXR register, an interrupt is generated if RIE=1 in the UCR2 register. If one or more errors are detected in the received word, the appropriate receive-related flags NF, FERR, and/or PERR are set within the same clock cycle. The b7 PERR NF FERR OERR R ID L E R X IF T ID L E b0 RIDLE The RIDLE flag is the receiver status flag. When this read only flag is 0 it indicates that the receiver is between the initial detection of the start bit and the completion of the stop bit. When the flag is 1 it indicates that the receiver is idle. Between the completion of the stop bit and the detection of the next start bit, the RIDLE bit is 1 indicating that the UART is idle. OERR The OERR flag is the overrun error flag, which indicates when the receiver buffer has overflowed. When this read only flag is 0 there is no overrun error. When the flag is 1 an overrun error occurs which will inhibit further transfers to the RXR receive data register. The flag is cleared by a software sequence, which is a read to the status register USR followed by an access to the RXR data register. FERR The FERR flag is the framing error flag. When this read only flag is 0 it indicates no framing error. When the flag is 1 it indicates that a framing error has been detected for the current character. The flag can also be cleared by a software sequence which will involve a read to the USR status register followed by an access to the RXR data register. NF The NF flag is the noise flag. When this read only flag is 0 it indicates a no noise condition. When the flag is 1 it indicates that the UART has detected noise on the receiver input. The NF flag is set during the same cycle as the RXIF flag but will not be set in the case of an overrun. The NF flag can be cleared by a software sequence which will involve a read to the USR status register, followed by an access to the RXR data register. USR R e g is te r T X IF T r a n s m it d a ta r e g is te r e m p ty 1 : c h a r a c te r tr a n s fe r r e d to tr a n s m it s h ift r e g is te r 0 : c h a r a c te r n o t tr a n s fe r r e d to tr a n s m it s h ift r e g is te r T r a n s m is s io n id le 1 : n o tr a n s m is s io n in p r o g r e s s 0 : tr a n s m is s io n in p r o g r e s s R e c e iv e R X R r e g is te r s ta tu s 1 : R X R r e g is te r h a s a v a ila b le d a ta 0 : R X R r e g is te r is e m p ty R e c e iv e r s ta tu s 1 : r e c e iv e r is id le 0 : d a ta b e in g r e c e iv e d O v e rru n e rro r 1 : o v e rru n e rro r d e te c te d 0 : n o o v e rru n e rro r d e te c te d F r a m in g e r r o r fla g 1 : fr a m in g e r r o r d e te c te d 0 : n o fr a m in g e r r o r N o is e fla g 1 : n o is e d e te c te d 0 : n o n o is e d e te c te d P a r ity e r r o r fla g 1 : p a r ity e r r o r d e te c te d 0 : n o p a r ity e r r o r d e te c te d Rev. 1.30 33 March 9, 2007 HT46RU25/HT46CU25 PERR The PERR flag is the parity error flag. When this read only flag is 0 it indicates that a parity error has not been detected. When the flag is 1 it indicates that the parity of the received word is incorrect. This error flag is applicable only if Parity mode (odd or even) is selected. The flag can also be cleared by a software sequence which involves a read to the USR status register, followed by an access to the RXR data register. used, if the bit is equal to 0 then only one stop bit is used. PRT This is the parity type selection bit. When this bit is equal to 1 odd parity will be selected, if the bit is equal to 0 then even parity will be selected. PREN This is parity enable bit. When this bit is equal to 1 the parity function will be enabled, if the bit is equal to 0 then the parity function will be disabled. BNO This bit is used to select the data length format, which can have a choice of either 8-bits or 9-bits. If this bit is equal to 1 then a 9-bit data length will be selected, if the bit is equal to 0 then an 8-bit data length will be selected. If 9-bit data length is selected then bits RX8 and TX8 will be used to store the 9th bit of the received and transmitted data respectively. UARTEN The UARTEN bit is the UART enable bit. When the bit is 0 the UART will be disabled and the RX and TX pins will function as General Purpose I/O pins. When the bit is 1 the UART will be enabled and the TX and RX pins will function as defined by the TXEN and RXEN control bits. When the UART is disabled it will empty the buffer so any character remaining in the buffer will be discarded. In addition, the baud rate counter value will be reset. When the UART is disabled, all error and status flags will be reset. The TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR, and NF bits will be cleared, while the TIDLE, TXIF and RIDLE bits will be set. Other control bits in UCR1, UCR2, and BRG registers will remain unaffected. If the UART is active and the UARTEN bit is cleared, all pending transmissions and receptions will be terminated and the module will be reset as defined above. When the UART is re-enabled it will restart in the same configuration. * UCR1 register The UCR1 register together with the UCR2 register are the two UART control registers that are used to set the various options for the UART function, such as overall on/off control, parity control, data transfer bit length etc. Further explanation on each of the bits is given below: TX8 This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the transmitted data, known as TX8. The BNO bit is used to determine whether data transfers are in 8-bit or 9-bit format. RX8 This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data, known as RX8. The BNO bit is used to determine whether data transfers are in 8-bit or 9-bit format. TXBRK The TXBRK bit is the Transmit Break Character bit. When this bit is 0 there are no break characters and the TX pin operates normally. When the bit is 1 there are transmit break characters and the transmitter will send logic zeros. When equal to 1 after the buffered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the TXBRK bit is reset. STOPS This bit determines if one or two stop bits are to be used. When this bit is equal to 1 two stop bits are b7 UARTEN BNO PREN PRT STOPS TXBRK RX8 b0 TX8 U C R 1 R e g is te r T r a n s m it d a ta b it 8 ( w r ite o n ly ) R e c e iv e d a ta b it 8 ( r e a d o n ly ) T r a n s m it b r e a k c h a r a c te r 1 : tr a n s m it b r e a k c h a r a c te r s 0 : n o b re a k c h a ra c te rs D e fin e s th e n u m b e r o f s to p b its 1 : tw o s to p b its 0 : o n e s to p b it P a r ity ty p e b it 1 : o d d p a r ity fo r p a r ity g e n e r a to r 0 : e v e n p a r ity fo r p a r ity g e n e r a to r P a r ity e n a b le b it 1 : p a r ity fu n c tio n e n a b le d 0 : p a r ity fu n c tio n d is a b le d N u m b e r o f d a ta tr a n s fe r b its 1 : 9 - b it d a ta tr a n s fe r 0 : 8 - b it d a ta tr a n s fe r U A R T e n a b le b it 1 : e n a b le U A R T , T X & R X p in s a s U A R T p in s 0 : d is a b le U A R T , T X & R X p in s a s I/O p o r t p in s Rev. 1.30 34 March 9, 2007 HT46RU25/HT46CU25 * UCR2 register The UCR2 register is the second of the two UART control registers and serves several purposes. One of its main functions is to control the basic enable/disable operation of the UART Transmitter and Receiver as well as enabling the various UART interrupt sources. The register also serves to control the baud rate speed, receiver wake-up enable and the address detect enable. Further explanation on each of the bits is given below: to 0 and if the MCU is in the Power Down Mode, any edge transitions on the RX pin will not wake-up the device. TEIE This bit enables or disables the transmitter empty interrupt. If this bit is equal to 1 when the transmitter empty TXIF flag is set, due to a transmitter empty condition, the UART interrupt request flag will be set. If this bit is equal to 0 the UART interrupt request flag will not be influenced by the condition of the TXIF flag. TIIE This bit enables or disables the transmitter idle interrupt. If this bit is equal to 1 when the transmitter idle TIDLE flag is set, the UART interrupt request flag will be set. If this bit is equal to 0 the UART interrupt request flag will not be influenced by the condition of the TIDLE flag. RIE This bit enables or disables the receiver interrupt. If this bit is equal to 1 when the receiver overrun OERR flag or receive data available RXIF flag is set, the UART interrupt request flag will be set. If this bit is equal to 0 the UART interrupt will not be influenced by the condition of the OERR or RXIF flags. WAKE This bit enables or disables the receiver wake-up function. If this bit is equal to 1 and if the MCU is in the Power Down Mode, a low going edge on the RX input pin will wake-up the device. If this bit is equal b7 TXEN RXEN BRGH ADDEN W AKE R IE T IIE b0 ADDEN The ADDEN bit is the address detect mode bit. When this bit is 1 the address detect mode is enabled. When this occurs, if the 8th bit, which corresponds to RX7 if BNO=0, or the 9th bit, which corresponds to RX8 if BNO=1, has a value of 1 then the received word will be identified as an address, rather than data. If the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8 or 9 bit depending on the value of BNO. If the address bit is 0 an interrupt will not be generated, and the received data will be discarded. BRGH The BRGH bit selects the high or low speed mode of the Baud Rate Generator. This bit, together with the value placed in the BRG register, controls the Baud Rate of the UART. If this bit is equal to 1 the high speed mode is selected. If the bit is equal to 0 the low speed mode is selected. RXEN The RXEN bit is the Receiver Enable Bit. When this bit is equal to 0 the receiver will be disabled with any pending data receptions being aborted. In addition the buffer will be reset. In this situation the RX pin can be used as a general purpose I/O pin. If the RXEN bit is equal to 1 the receiver will be enabled and if the UARTEN bit is equal to 1 the RX pin will be controlled by the UART. Clearing the RXEN bit during a transmission will cause the data reception to be aborted and will reset the receiver. If this occurs, the RX pin can be used as a general purpose I/O pin. T E IE U C R 2 R e g is te r T r a n s m itte r e m p ty in te r r u p t e n a b le 1 : T X IF in te r r u p t r e q u e s t e n a b le 0 : T X IF in te r r u p t r e q u e s t d is a b le T r a n s m itte r id le in te r r u p t e n a b le 1 : T ID L E in te r r u p t r e q u e s t e n a b le 0 : T ID L E in te r r u p t r e q u e s t d is a b le R e c e iv e r in te r r u p t e n a b le 1 : R X IF in te r r u p t r e q u e s t e n a b le 0 : R X IF in te r r u p t r e q u e s t d is a b le D e fin e s th e R X w a k e u p e n a b le 1 : R X w a k e u p e n a b le ( fa llin g e d g e ) 0 : R X w a k e u p d is a b le A d d re s s d e te c t m o d e 1 : e n a b le 0 : d is a b le H ig h b a u d r a te s e le c t b it 1 : h ig h s p e e d 0 : lo w s p e e d R e c e iv e r e n a b le b it 1 : r e c e iv e r e n a b le 0 : r e c e iv e r d is a b le T r a n s m itte r e n a b le b it 1 : tr a n s m itte r e n a b le 0 : tr a n s m itte r d is a b le Rev. 1.30 35 March 9, 2007 HT46RU25/HT46CU25 TXEN The TXEN bit is the Transmitter Enable Bit. When this bit is equal to 0 the transmitter will be disabled with any pending transmissions being aborted. In addition the buffer will be reset. In this situation the TX pin can be used as a general purpose I/O pin. If the TXEN bit is equal to 1 the transmitter will be enabled and if the UARTEN bit is equal to 1 the TX pin will be controlled by the UART. Clearing the TXEN bit during a transmission will cause the transmission to be aborted and will reset the transmitter. If this occurs, the TX pin can be used as a general purpose I/O pin. By programming the BRGH bit which allows selection of the related formula and programming the required value in the BRG register, the required baud rate can be setup. Note that because the actual baud rate is determined using a discrete value, N, placed in the BRG register, there will be an error associated between the actual and requested value. The following example shows how the BRG register value N and the error value can be calculated. Calculating the register and error values For a clock frequency of 8MHz, and with BRGH set to 0 determine the BRG register value N, the actual baud rate and the error value for a desired baud rate of 9600. From the above table the desired baud rate BR fSYS = [64 (N+1)] fSYS Re-arranging this equation gives N = -1 (BRx64) 8000000 - 1 = 12.0208 Giving a value for N = (9600x 64) To obtain the closest value, a decimal value of 12 should be placed into the BRG register. This gives an actual or calculated baud rate value of 8000000 BR = = 9615 [64(12+1)] Therefore the error is equal to = 0.16% * Baud rate generator To setup the speed of the serial data communication, the UART function contains its own dedicated baud rate generator. The baud rate is controlled by its own internal free running 8-bit timer, the period of which is determined by two factors. The first of these is the value placed in the BRG register and the second is the value of the BRGH bit within the UCR2 control register. The BRGH bit decides, if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. The value in the BRG register determines the division factor, N, which is used in the following baud rate calculation formula. Note that N is the decimal value placed in the BRG register and has a range of between 0 and 255. UCR2 BRGH Bit Baud Rate 0 fSYS [64 (N+1)] 1 fSYS [16 (N+1)] The following tables show actual values of baud rate and error values for the two values of BRGH. Baud Rate K/BPS 0.3 1.2 2.4 4.8 9.6 19.2 38.4 57.6 115.2 Baud Rates for BRGH=0 fSYS=8MHz BRG 3/4 103 51 25 12 6 2 1 0 Kbaud 3/4 1.202 2.404 4.807 9.615 17.857 41.667 62.5 125 Error 3/4 0.16 0.16 0.16 0.16 -6.99 8.51 8.51 8.51 fSYS=7.159MHz BRG 3/4 92 46 22 11 5 2 1 0 Kbaud 3/4 1.203 2.38 4.863 9.322 18.64 37.29 55.93 111.86 Error 3/4 0.23 -0.83 1.32 -2.9 -2.9 -2.9 -2.9 -2.9 BRG 207 51 25 12 6 2 1 0 3/4 fSYS=4MHz Kbaud 0.300 1.202 2.404 4.808 8.929 20.83 3/4 62.5 3/4 Error 0.00 0.16 0.16 0.16 -6.99 8.51 3/4 8.51 3/4 fSYS=3.579545MHz BRG 185 46 22 11 5 2 1 0 3/4 Kbaud 0.300 1.19 2.432 4.661 9.321 18.643 3/4 55.93 3/4 Error 0.00 -0.83 1.32 -2.9 -2.9 -2.9 3/4 -2.9 3/4 Baud Rates and Error Values for BRGH = 0 Rev. 1.30 36 March 9, 2007 HT46RU25/HT46CU25 Baud Rate K/BPS 0.3 1.2 2.4 4.8 9.6 19.2 38.4 57.6 115.2 250 Baud Rates for BRGH=1 fSYS=8MHz BRG 3/4 3/4 207 103 51 25 12 8 3 1 Kbaud 3/4 3/4 2.404 4.808 9.615 19.231 38.462 55.556 125 250 Error 3/4 3/4 0.16 0.16 0.16 0.16 0.16 -3.55 8.51 0 fSYS=7.159MHz BRG 3/4 3/4 185 92 46 22 11 7 3 3/4 Kbaud 3/4 3/4 2.405 4.811 9.520 19.454 37.287 55.93 111.86 3/4 Error 3/4 3/4 0.23 0.23 -0.832 1.32 -2.9 -2.9 -2.9 3/4 BRG 3/4 207 103 51 25 12 6 3 1 0 fSYS=4MHz Kbaud 3/4 1.202 2.404 4.808 9.615 19.231 35.714 62.5 125 250 Error 3/4 0.16 0.16 0.16 0.16 0.16 -6.99 8.51 8.51 0 fSYS=3.579545MHz BRG 3/4 185 92 46 22 11 5 3 1 3/4 Kbaud 3/4 1.203 2.406 4.76 9.727 18.643 37.286 55.930 111.86 3/4 Error 3/4 0.23 0.23 -0.83 1.32 -2.9 -2.9 -2.9 -2.9 3/4 Baud Rates and Error Values for BRGH = 1 * Setting up and controlling the UART Introduction For data transfer, the UART function utilizes a non-return-to-zero, more commonly known as NRZ, format. This is composed of one start bit, eight or nine data bits, and one or two stop bits. Parity is supported by the UART hardware, and can be setup to be even, odd or no parity. For the most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1, is used as the default setting, which is the setting at power-on. The number of data bits and stop bits, along with the parity, are setup by programming the corresponding BNO, PRT, PREN, and STOPS bits in the UCR1 register. The baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator, while the data is transmitted and received LSB first. Although the UARTs transmitter and receiver are functionally independent, they both use the same data format and baud rate. In all cases stop bits will be used for data transmission. Enabling/disabling the UART The basic on/off function of the internal UART function is controlled using the UARTEN bit in the UCR1 register. As the UART transmit and receive pins, TX and RX respectively, are pin-shared with normal I/O pins, one of the basic functions of the UARTEN control bit is to control the UART function of these two pins. If the UARTEN, TXEN and RXEN bits are set, then these two I/O pins will be setup as a TX output pin and an RX input pin respectively, in effect disabling the normal I/O pin function. If no data is being transmitted on the TX pin then it will default to a logic high value. Clearing the UARTEN bit will disable the TX and RX pins and allow these two pins to be used as normal I/O pins. When the UART function is disabled the buffer will be reset to an empty condition, at the same time discarding any remaining residual data. Disabling the UART will also reset the error and status flags with bits TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF being cleared while bits TIDLE, TXIF and RIDLE will be set. The remaining control bits in the UCR1, UCR2 and BRG registers will remain unaffected. If the UARTEN bit in the UCR1 register is cleared while the UART is active, then all pending transmissions and receptions will be immediately suspended and the UART will be reset to a condition as defined above. If the UART is then subsequently re-enabled, it will restart again in the same configuration. Data, parity and stop bit selection The format of the data to be transferred, is composed of various factors such as data bit length, parity on/off, parity type, address bits and the number of stop bits. These factors are determined by the setup of various bits within the UCR1 register. The BNO bit controls the number of data bits which can be set to either 8 or 9, the PRT bit controls the choice of odd or even parity, the PREN bit controls the parity on/off function and the STOPS bit decides whether one or two stop bits are to be used. The following table shows various formats for data transmission. The address bit identifies the frame as an address character. The number of stop bits, which can be either one or two, is independent of the data length. Rev. 1.30 37 March 9, 2007 HT46RU25/HT46CU25 Start Bit Data Bits Address Bits Parity Bits Stop Bit Example of 8-bit Data Formats 1 1 1 8 7 7 0 0 1 1 0 1 0 1 1 1 Example of 9-bit Data Formats 1 1 1 9 8 8 0 0 11 0 1 0 1 1 1 Transmitting data When the UART is transmitting data, the data is shifted on the TX pin from the shift register, with the least significant bit first. In the transmit mode, the TXR register forms a buffer between the internal bus and the transmitter shift register. It should be noted that if 9-bit data format has been selected, then the MSB will be taken from the TX8 bit in the UCR1 register. The steps to initiate a data transfer can be summarized as follows: - Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word length, parity type and number of stop bits. Setup the BRG register to select the desired baud rate. Set the TXEN bit to ensure that the TX pin is used as a UART transmitter pin and not as an I/O pin. Access the USR register and write the data that is to be transmitted into the TXR register. Note that this step will clear the TXIF bit. This sequence of events can now be repeated to send additional data. - Transmitter Receiver Data Format The following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats. * UART transmitter Data word lengths of either 8 or 9 bits, can be selected by programming the BNO bit in the UCR1 register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9th bit, which is the MSB, needs to be stored in the TX8 bit in the UCR1 register. At the transmitter core lies the Transmitter Shift Register, more commonly known as the TSR, whose data is obtained from the transmit data register, which is known as the TXR register. The data to be transmitted is loaded into this TXR register by the application program. The TSR register is not written to with new data until the stop bit from the previous transmission has been sent out. As soon as this stop bit has been transmitted, the TSR can then be loaded with new data from the TXR register, if it is available. It should be noted that the TSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. An actual transmission of data will normally be enabled when the TXEN bit is set, but the data will not be transmitted until the TXR register has been loaded with data and the baud rate generator has defined a shift clock source. However, the transmission can also be initiated by first loading data into the TXR register, after which the TXEN bit can be set. When a transmission of data begins, the TSR is normally empty, in which case a transfer to the TXR register will result in an immediate transfer to the TSR. If during a transmission the TXEN bit is cleared, the transmission will immediately cease and the transmitter will be reset. The TX output pin will then return to having a normal general purpose I/O pin function. - It should be noted that when TXIF=0, data will be inhibited from being written to the TXR register. Clearing the TXIF flag is always achieved using the following software sequence: 1. A USR register access 2. A TXR register write execution The read-only TXIF flag is set by the UART hardware and if set indicates that the TXR register is empty and that other data can now be written into the TXR register without overwriting the previous data. If the TEIE bit is set then the TXIF flag will generate an interrupt. During a data transmission, a write instruction to the TXR register will place the data into the TXR register, which will be copied to the shift register at the end of the present transmission. When there is no data transmission in progress, a write instruction to the TXR register will place the data directly into the shift register, resulting in the commencement of data transmission, and the TXIF bit being immediately set. When a frame transmission is complete, which happens after stop bits are sent or after the break frame, the TIDLE bit will be set. To clear the TIDLE bit the following software sequence is used: 1. A USR register access 2. A TXR register write execution Note that both the TXIF and TIDLE bits are cleared by the same software sequence. P a r ity B it N ext S ta rt B it S ta r t B it B it 0 B it 1 B it 2 B it 3 B it 4 B it 5 B it 6 B it 7 S to p B it 8 -B it D a ta F o r m a t P a r ity B it S ta r t B it B it 0 B it 1 B it 2 B it 3 B it 4 B it 5 B it 6 B it 7 B it 8 S to p B it N ext S ta rt B it 9 -B it D a ta F o r m a t Rev. 1.30 38 March 9, 2007 HT46RU25/HT46CU25 Transmit break If the TXBRK bit is set then break characters will be sent on the next transmission. Break character transmission consists of a start bit, followed by 13 N 0 bits and stop bits, where N=1, 2, etc. If a break character is to be transmitted then the TXBRK bit must be first set by the application program, then cleared to generate the stop bits. Transmitting a break character will not generate a transmit interrupt. Note that a break condition length is at least 13 bits long. If the TXBRK bit is continually kept at a logic high level then the transmitter circuitry will transmit continuous break characters. After the application program has cleared the TXBRK bit, the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits. The automatic logic highs at the end of the last break character will ensure that the start bit of the next frame is recognized. - Set the RXEN bit to ensure that the RX pin is used as a UART receiver pin and not as an I/O pin. At this point the receiver will be enabled which will begin to look for a start bit. When a character is received the following sequence of events will occur: - The RXIF bit in the USR register will be set when RXR register has data available, at least one more character can be read. When the contents of the shift register have been transferred to the RXR register, then if the RIE bit is set, an interrupt will be generated. If during reception, a frame error, noise error, parity error, or an overrun error has been detected, then the error flags can be set. - - * UART receiver The RXIF bit can be cleared using the following software sequence: 1. A USR register access 2. An RXR register read execution Introduction The UART is capable of receiving word lengths of either 8 or 9 bits. If the BNO bit is set, the word length will be set to 9 bits with the MSB being stored in the RX8 bit of the UCR1 register. At the receiver core lies the Receive Serial Shift Register, commonly known as the RSR. The data which is received on the RX external input pin, is sent to the data recovery block. The data recovery block operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the baud rate. After the RX pin is sampled for the stop bit, the received data in RSR is transferred to the receive data register, if the register is empty. The data which is received on the external RX input pin is sampled three times by a majority detect circuit to determine the logic level that has been placed onto the RX pin. It should be noted that the RSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. Receiving data When the UART receiver is receiving data, the data is serially shifted in on the external RX input pin, LSB first. In the read mode, the RXR register forms a buffer between the internal bus and the receiver shift register. The RXR register is a two byte deep FIFO data buffer, where two bytes can be held in the FIFO while a third byte can continue to be received. Note that the application program must ensure that the data is read from RXR before the third byte has been completely shifted in, otherwise this third byte will be discarded and an overrun error OERR will be subsequently indicated. The steps to initiate a data transfer can be summarized as follows: - Receive break Any break character received by the UART will be managed as a framing error. The receiver will count and expect a certain number of bit times as specified by the values programmed into the BNO and STOPS bits. If the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specified by BNO and STOPS. The RXIF bit is set, FERR is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the RIDLE bit is set. If a long break signal has been detected and the receiver has received a start bit, the data bits and the invalid stop bit, which sets the FERR flag, the receiver must wait for a valid stop bit before looking for the next start bit. The receiver will not make the assumption that the break condition on the line is the next start bit. A break is regarded as a character that contains only zeros with the FERR flag set. The break character will be loaded into the buffer and no further data will be received until stop bits are received. It should be noted that the RIDLE read only flag will go high when the stop bits have not yet been received. The reception of a break character on the UART registers will result in the following: - The framing error flag, FERR, will be set. The receive data register, RXR, will be cleared. The OERR, NF, PERR, RIDLE or RXIF flags will possibly be set. Make the correct selection of BNO, PRT, PREN and STOPS bits to define the word length, parity type and number of stop bits. Setup the BRG register to select the desired baud rate. - Idle status When the receiver is reading data, which means it will be in between the detection of a start bit and the reading of a stop bit, the receiver status flag in the USR register, otherwise known as the RIDLE flag, will have a zero value. In between the reception of a stop bit and the detection of the next start bit, the RIDLE flag will have a high value, which indicates the receiver is in an idle condition. Rev. 1.30 39 March 9, 2007 HT46RU25/HT46CU25 Receiver interrupt The read only receive interrupt flag RXIF in the USR register is set by an edge generated by the receiver. An interrupt is generated if RIE=1, when a word is transferred from the Receive Shift Register, RSR, to the Receive Data Register, RXR. An overrun error can also generate an interrupt if RIE=1. - No interrupt will be generated. However this bit rises at the same time as the RXIF bit which itself generates an interrupt. Note that the NF flag is reset by a USR register read operation followed by an RXR register read operation. * Managing receiver errors Several types of reception errors can occur within the UART module, the following section describes the various types and how they are managed by the UART. Overrun Error - OERR flag The RXR register is composed of a two byte deep FIFO data buffer, where two bytes can be held in the FIFO register, while a third byte can continue to be received. Before this third byte has been entirely shifted in, the data should be read from the RXR register. If this is not done, the overrun error flag OERR will be consequently indicated. In the event of an overrun error occurring, the following will happen: - Framing Error - FERR Flag The read only framing error flag, FERR, in the USR register, is set if a zero is detected instead of stop bits. If two stop bits are selected, both stop bits must be high, otherwise the FERR flag will be set. The FERR flag is buffered along with the received data and is cleared on any reset. Parity Error - PERR Flag The read only parity error flag, PERR, in the USR register, is set if the parity of the received word is incorrect. This error flag is only applicable if the parity is enabled, PREN = 1, and if the parity type, odd or even is selected. The read only PERR flag is buffered along with the received data bytes. It is cleared on any reset. It should be noted that the FERR and PERR flags are buffered along with the corresponding word and should be read before reading the data word. The OERR flag in the USR register will be set. The RXR contents will not be lost. The shift register will be overwritten. * UART interrupt scheme An interrupt will be generated if the RIE bit is set. The OERR flag can be cleared by an access to the USR register followed by a read to the RXR register. Noise Error - NF Flag Over-sampling is used for data recovery to identify valid incoming data and noise. If noise is detected within a frame the following will occur: - The read only noise flag, NF, in the USR register will be set on the rising edge of the RXIF bit. Data will be transferred from the Shift register to the RXR register. The UART internal function possesses its own internal interrupt and independent interrupt vector. Several individual UART conditions can generate an internal UART interrupt. These conditions are, a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. When any of these conditions are created, if the UART interrupt is enabled and the stack is not full, the program will jump to the UART interrupt vector where it can be serviced before returning to the main program. Four of these conditions, have a corresponding USR register flag, which will generate a UART interrupt if its associated interrupt enable flag in USR R e g is te r U C R 2 R e g is te r T E IE 1 0 IN T C 1 R e g is te r 0 1 R IE 1 0 U A R T In te rru p t R e q u e s t F la g URF EURI IN T C 0 R e g is te r EMI T r a n s m itte r E m p ty F la g T X IF T r a n s m itte r Id le F la g T ID L E T IIE R e c e iv e r O v e r r u n F la g O E R R OR R e c e iv e r D a ta A v a ila b le R X IF ADDEN 1 0 0 1 R X P in W a k e -u p W AKE 1 0 R X 7 if B N O = 0 R X 8 if B N O = 1 U C R 2 R e g is te r UART Interrupt Scheme Rev. 1.30 40 March 9, 2007 HT46RU25/HT46CU25 the UCR2 register is set. The two transmitter interrupt conditions have their own corresponding enable bits, while the two receiver interrupt conditions have a shared enable bit. These enable bits can be used to mask out individual UART interrupt sources. The address detect condition, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt when an address detect condition occurs if its function is enabled by setting the ADDEN bit in the UCR2 register. An RX pin wake-up, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt if the microcontroller is woken up by a low going edge on the RX pin, if the WAKE and RIE bits in the UCR2 register are set. Note that in the event of an RX wake-up interrupt occurring, there will be a delay of 1024 system clock cycles before the system resumes normal operation. Note that the USR register flags are read only and cannot be cleared or set by the application program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the case for some of the other interrupts. The flags will be cleared automatically when certain actions are taken by the UART, the details of which are given in the UART register section. The overall UART interrupt can be disabled or enabled by the EURI bit in the INTC1 interrupt control register to prevent a UART interrupt from occurring. * Address detect mode ADDEN 0 Bit 9 if BNO=1, UART Interrupt Bit 8 if BNO=0 Generated 0 1 0 O O X O 1 1 ADDEN Bit Function * UART operation in power down mode Setting the Address Detect Mode bit, ADDEN, in the UCR2 register, enables this special mode. If this bit is enabled then an additional qualifier will be placed on the generation of a Receiver Data Available interrupt, which is requested by the RXIF flag. If the ADDEN bit is enabled, then when data is available, an interrupt will only be generated, if the highest received bit has a high value. Note that the EURI and EMI interrupt enable bits must also be enabled for correct interrupt generation. This highest address bit is the 9th bit if BNO=1 or the 8th bit if BNO=0. If this bit is high, then the received word will be defined as an address rather than data. A Data Available interrupt will be generated every time the last bit of the received word is set. If the ADDEN bit is not enabled, then a Receiver Data Available interrupt will be generated each time the RXIF flag is set, irrespective of the data last bit status. The address detect mode and parity enable are mutually exclusive functions. Therefore if the address detect mode is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity enable bit to zero. When the MCU is in the Power Down Mode the UART will cease to function. When the device enters the Power Down Mode, all clock sources to the module are shutdown. If the MCU enters the Power Down Mode while a transmission is still in progress, then the transmission will be terminated and the external TX transmit pin will be forced to a logic high level. In a similar way, if the MCU enters the Power Down Mode while receiving data, then the reception of data will likewise be terminated. When the MCU enters the Power Down Mode, note that the USR, UCR1, UCR2, transmit and receive registers, as well as the BRG register will not be affected. The UART function contains a receiver RX pin wake-up function, which is enabled or disabled by the WAKE bit in the UCR2 register. If this bit, along with the UART enable bit, UARTEN, the receiver enable bit, RXEN and the receiver interrupt bit, RIE, are all set before the MCU enters the Power Down Mode, then a falling edge on the RX pin will wake-up the MCU from the Power Down Mode. Note that as it takes 1024 system clock cycles after a wake-up, before normal microcontroller operation resumes, any data received during this time on the RX pin will be ignored. For a UART wake-up interrupt to occur, in addition to the bits for the wake-up being set, the global interrupt enable bit, EMI, and the UART interrupt enable bit, EURI must also be set. If these two bits are not set then only a wake up event will occur and no interrupt will be generated. Note also that as it takes 1024 system clock cycles after a wake-up before normal microcontroller resumes, the UART interrupt will not be generated until after this time has elapsed. Rev. 1.30 41 March 9, 2007 HT46RU25/HT46CU25 Options The following shows the kinds of options in the device. ALL the options must be defined to ensure a proper functioning system. Options OSC type selection. This option is to determine whether an RC or crystal or 32768Hz crystal oscillator is chosen as a system clock. If 32768Hz crystal oscillator is chosen as system clock or as fS, the PC6 and PC7 will be used as oscillator pins. WDT, RTC and Time Base clock source selection. There are three types of selections: system clock/4 or RTC OSC or WDT OSC. WDT enable/disable selection. WDT can be enabled or disabled by option. CLRWDT times selection. This option defines how to clear the WDT by instruction. One time means that the CLR WDT instruction can clear the WDT. Two times means only if both of the CLR WDT1 and CLR WDT2 instructions have been executed, then WDT can be cleared. Time Base time-out period selection. The Time Base time-out period ranges from 212/fS to 215/fS. fS means the clock source selected by options. Wake-up selection. This option defines the wake-up function activity. External I/O pins (PA only) all have the capability to wake-up the device from a HALT by a falling edge. (Bit option) Pull-high selection. This option is to determine whether a pull-high resistance is visible or not in the input mode of the I/O ports. PA and PB are bit option; PC, PD, PF and PG are port option. PFD selection. PA3: level output or PFD0 (Timer0) output or PFD1 (Timer1) PWM selection: (7+1) or (6+2) mode PD0: level output or PWM0 output PD1: level output or PWM1 output PD2: level output or PWM2 output PD3: level output or PWM3 output WDT time-out period selection. 212/fS~213/fS, 213/fS~214/fS, 214/fS~215/fS, 215/fS~216/fS. I2C Bus function: enable or disable LVR selection. LVR has enable or disable options Rev. 1.30 42 March 9, 2007 HT46RU25/HT46CU25 Application Circuits V DD 0 .0 1 m F * 100kW 0 .1 m F 10kW VDD RES PA0~PA2 P A 3 /P F D PA4 P A 5 /IN T P A 6 /S D A P A 7 /S C L P B 0 /A N 0 P B 7 /A N 7 P C 0 /T X P C 1 /R X PC 2~PC 5 P C 6 /O S C 3 V DD 0 .1 m F * VSS ~ OSC C ir c u it S e e R ig h t S id e 32768H z OSC1 OSC2 OSC3 P C 7 /O S C 4 P D 0 /P W M 0 R 470pF OSC OSC1 fS YS R C S y s te m O s c illa to r 30kW P D 3 /P W M 3 PD 4~PD 7 C1 /4 TM R0 TM R1 TM R2 PF0~PF7 PG 0~PG 7 C2 OSC2 H T 4 6 R U 2 5 /H T 4 6 C U 2 5 The following table shows the C1 and C2 values corresponding to the different crystal values. (For reference only) Crystal or Resonator 4MHz Crystal 4MHz Resonator 3.58MHz Crystal 3.58MHz Resonator 2MHz Crystal & Resonator 1MHz Crystal 480kHz Resonator 455kHz Resonator 429kHz Resonator C1, C2 0pF 10pF 0pF 25pF 25pF 35pF 300pF 300pF 300pF ~ OSC2 OSC1 C ry s ta l S y s te m F o r th e v a lu e s , s e e ta b le b e lo w O s c illa to r O S C C ir c u it Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. Rev. 1.30 43 March 9, 2007 HT46RU25/HT46CU25 Instruction Set Summary Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z Rev. 1.30 44 March 9, 2007 HT46RU25/HT46CU25 Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected (1) : If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. (2) (3) (1) (4) Rev. 1.30 45 March 9, 2007 HT46RU25/HT46CU25 Instruction Definition ADC A,[m] Description Operation Affected flag(s) TO 3/4 ADCM A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,x Description Operation Affected flag(s) TO 3/4 ADDM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m] Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m] Rev. 1.30 46 March 9, 2007 HT46RU25/HT46CU25 AND A,[m] Description Operation Affected flag(s) TO 3/4 AND A,x Description Operation Affected flag(s) TO 3/4 ANDM A,[m] Description Operation Affected flag(s) TO 3/4 CALL addr Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m] Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m] Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack Program Counter+1 Program Counter addr TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) CLR [m] Description Operation Affected flag(s) Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Rev. 1.30 47 March 9, 2007 HT46RU25/HT46CU25 CLR [m].i Description Operation Affected flag(s) TO 3/4 CLR WDT Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0 Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. WDT 00H PDF and TO 0 TO 0 PDF 0 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) CLR WDT1 Description Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) CLR WDT2 Description Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) CPL [m] Description Operation Affected flag(s) Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m] TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Rev. 1.30 48 March 9, 2007 HT46RU25/HT46CU25 CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m] TO 3/4 DAA [m] Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Operation Affected flag(s) Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Operation Affected flag(s) DEC [m] Description Operation Affected flag(s) Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 DECA [m] Description Operation Affected flag(s) Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Rev. 1.30 49 March 9, 2007 HT46RU25/HT46CU25 HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. Program Counter Program Counter+1 PDF 1 TO 0 TO 0 INC [m] Description Operation Affected flag(s) TO 3/4 INCA [m] Description Operation Affected flag(s) TO 3/4 JMP addr Description Operation Affected flag(s) TO 3/4 MOV A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Program Counter addr PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 1 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1 Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1 Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m] Rev. 1.30 50 March 9, 2007 HT46RU25/HT46CU25 MOV A,x Description Operation Affected flag(s) TO 3/4 MOV [m],A Description Operation Affected flag(s) TO 3/4 NOP Description Operation Affected flag(s) TO 3/4 OR A,[m] Description Operation Affected flag(s) TO 3/4 OR A,x Description Operation Affected flag(s) TO 3/4 ORM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. Program Counter Program Counter+1 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m] Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m] Rev. 1.30 51 March 9, 2007 HT46RU25/HT46CU25 RET Description Operation Affected flag(s) TO 3/4 RET A,x Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. Program Counter Stack Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Program Counter Stack ACC x TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RETI Description Operation Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Program Counter Stack EMI 1 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RL [m] Description Operation Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RLA [m] Description Operation Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) Rev. 1.30 52 March 9, 2007 HT46RU25/HT46CU25 RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7 TO 3/4 RLCA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Affected flag(s) Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Operation Affected flag(s) RR [m] Description Operation Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RRA [m] Description Operation Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RRC [m] Description Operation Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Affected flag(s) Rev. 1.30 53 March 9, 2007 HT46RU25/HT46CU25 RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0 TO 3/4 SBC A,[m] Description Operation Affected flag(s) TO 3/4 SBCM A,[m] Description Operation Affected flag(s) TO 3/4 SDZ [m] Description PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Operation Affected flag(s) Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) SDZA [m] Description Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) Rev. 1.30 54 March 9, 2007 HT46RU25/HT46CU25 SET [m] Description Operation Affected flag(s) TO 3/4 SET [m]. i Description Operation Affected flag(s) TO 3/4 SIZ [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1 Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) SIZA [m] Description Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) SNZ [m].i Description Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0 Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Rev. 1.30 55 March 9, 2007 HT46RU25/HT46CU25 SUB A,[m] Description Operation Affected flag(s) TO 3/4 SUBM A,[m] Description Operation Affected flag(s) TO 3/4 SUB A,x Description Operation Affected flag(s) TO 3/4 SWAP [m] Description Operation Affected flag(s) TO 3/4 SWAPA [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1 Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1 Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1 Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4 Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) Rev. 1.30 56 March 9, 2007 HT46RU25/HT46CU25 SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0 Operation Affected flag(s) TO 3/4 SZA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0 Operation Affected flag(s) TO 3/4 SZ [m].i Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0 Operation Affected flag(s) TO 3/4 TABRDC [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) TABRDL [m] Description Operation Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) Rev. 1.30 57 March 9, 2007 HT46RU25/HT46CU25 XOR A,[m] Description Operation Affected flag(s) TO 3/4 XORM A,[m] Description Operation Affected flag(s) TO 3/4 XOR A,x Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m] Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m] Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x Rev. 1.30 58 March 9, 2007 HT46RU25/HT46CU25 Package Information 48-pin SSOP (300mil) Outline Dimensions 48 A 25 B 1 C C' 24 G H a F D E Symbol A B C C D E F G H a Dimensions in mil Min. 395 291 8 613 85 3/4 4 25 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 25 3/4 3/4 3/4 3/4 Max. 420 299 12 637 99 3/4 10 35 12 8 Rev. 1.30 59 March 9, 2007 HT46RU25/HT46CU25 56-pin SSOP (300mil) Outline Dimensions 56 A 1 C C' 29 B 28 G H a F D E Symbol A B C C D E F G H a Dimensions in mil Min. 395 291 8 720 89 3/4 4 25 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 25 3/4 3/4 3/4 3/4 Max. 420 299 12 730 99 3/4 10 35 12 8 Rev. 1.30 60 March 9, 2007 HT46RU25/HT46CU25 Product Tape and Reel Specifications Reel Dimensions T2 D A B C T1 SSOP 48W Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301 1000.1 13+0.5 -0.2 20.5 32.2+0.3 -0.2 38.20.2 Rev. 1.30 61 March 9, 2007 HT46RU25/HT46CU25 Carrier Tape Dimensions P0 D E F W C B0 P1 t D1 P K2 A0 K1 SSOP 48W Symbol W P E F D D1 P0 P1 A0 B0 K1 K2 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 320.3 160.1 1.750.1 14.20.1 2 Min. 1.5+0.25 40.1 20.1 120.1 16.20.1 2.40.1 3.20.1 0.350.05 25.5 Rev. 1.30 62 March 9, 2007 HT46RU25/HT46CU25 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 86-21-6485-5560 Fax: 86-21-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holmate Semiconductor, Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holmate.com Copyright O 2007 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.30 63 March 9, 2007 |
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